• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 64 subscribers
  • Views 363 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LMG1205: Power management forum

LMG1205: LMG1205

Rahul Goel1
Intellectual 540 points
Part Number: LMG1205

Hey,

(First,Please Refer to my last related post) Then how to do we calculate the minimum load/resistance for a particular capacitance let's say 0.1 uf because in our case the the charging time was much higher than the theoretical calculated charging time,but it didn't worked.

Thanks in advance

Rahul.

  • 0
    TI__Guru**** 189401 points

    Hi, Rahul,

    Our office is closed for the US Thanksgiving holiday.

    Jeff will get back to you early next week.

  • 0 in reply to Don Dapkus
    Intellectual 540 points

    Hey,

    No Problem !!!

    By the way ,Happy ThanksGiving festive to all US citizens.

    Thanks and Regards

    Rahul  

  • 0
    TI__Genius 12990 points

    Hi Rahul,

    The bootstrap charging path for the bootstrap capacitor is from the VDD capacitor thru the bootstrap diode to the HB-HS capacitor. Also the HS thru the low side FET is the charging path. So the boot diode resistance plus low side FET on resistance and the bootstrap capacitor results in a time constant. t= Cboot x (Rd + Rdson). If the boot diode resistance is 0.5 Ohms and boot cap is 0.1uF. If we assume Rdson of 0.1 Ohms then the time constant is t=0.1uF x 0.6 Ohms = 0.06us to reach 67% of the charge voltage. The effective bootstrap capacitance will be, 2x Qg(VDD - Vf (boot diode). The bootstrap capacitance = 10x gate capacitance is a good guideline for the boot capacitance value. The load on the HS node discharges the HB-HS cap, in this example, if the load discharges the cap during an HS on time longer than 60ns then eventually the HB-HS cap could be depleted with enough switching cycles preventing the cap from replenishing.

    Are the following operating conditions for you application the same as the original question? The input voltage i.e Vds=12v,Vdd = 5v,load resistance on a single phase 570 ohms ,input frequency 10kHz @50% duty

    Thanks,

  • 0 in reply to Jeffrey Mueller
    Intellectual 540 points

    Hey Jeff,

    No ,as mentioned before the operating condition is :-

     Vds=12v,Vdd = 5v,load resistance on a single phase 10 ohms ,input frequency 10kHz @50% duty.

    The images of which were already uploaded.

    Thanks and Regards.

    Rahul

  • 0 in reply to Rahul Goel1
    TI__Genius 12990 points

    Hi Rahul,

    Thanks for the update,

    To clear up and summarize the previous post, we are trying to use the load resistor on HS as the bootstrap charging path instead of the typical low side synchronous FET. Typically a low side FET switching HS to ground during HO off time would solve our issue but we are relying on the resistors path to ground.

    However, attempting to find the minimum load resistance I chose to simulate this. Using the LMG1205 spice model default schematic and setting the frequency to 10khz I tested VBUS=12V to 80V and found that the minimum resistance which keeps the bootstrap charged is 1ohm.  See attachment for data analysis.

    If 1ohm will not work for your application is it possible to use a low side FET or even body diode to accomplish the bootstrap charging path?

    If not are we able to power HB-HS on a seperate supply?

    minimum load on HS - with 100nF bootcap.pdf

    Thanks,