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Hi Team,
My SSD customer has some question about the layout:
(They are planning to use TPS62827, TPS62825, TPS62135, TPS562219A, TPS56C215.)
1. Could you kindly provide the layout guide of the layer under inductance (LX) that should be empty or ground? Or any special pattern?
2. How to evaluate the change in inductance due to the layout of the PCB?
The customer has 8 layers in their design.
Thanks for your kindly help!
Jamie
hi,
The devices are belongs to different product lines, and the rules maybe different. Please put one device on one thread to ask support, thanks.