TPS3430-Q1: What is the correct state of WDO# before SET1 is turned on during system power up?

Philip Pun

Prodigy 30 points

Part Number: TPS3430-Q1

Fig 10 shows WDO# switches from 1 to 0 before SET1 = 1. Shouldn't it stay high until after SET1 =1?

Fig 22 shows WDO# at 1 after VDD power on until tRST + WDL(max)?

over 5 years ago

0 Abhinav.Sharma over 5 years ago

TI__Genius 9375 points

Hi Philip,

For figure 10, he WDO is timing out due to the watchdog timeout, what do you mean until after?

For figure 22, WDO does not assert until Trst + WDU max.

Thanks,
Abhinav.

0 Philip Pun over 5 years ago in reply to Abhinav.Sharma

Prodigy 30 points

Hi Abhinav,

In Fig 10, with SET1 = 0, shouldn't the watch dog timer should be disabled and WDO# = 1?

In our board, the SET1=0 until the system is ready to come out of reset. So its important that the WDO# doesn't go low until after SET1 is driven high.

That's what I needed to confirm.

Rgds … Philip

0 Abhinav.Sharma over 5 years ago in reply to Philip Pun

TI__Genius 9375 points

Hi Philip,

You're right, when the watchdog is disabled, the WDO result should be high regardless of WDI. I think your analysis of the diagram is correct and it is showing inconsistent information. I would advise taking the text in the datasheet as fact, the WDO should be high regardless of WDI when the watchdog is disabled.

Thanks,
Abhinav.

0 Philip Pun over 5 years ago in reply to Abhinav.Sharma

Prodigy 30 points

Great. Thank you!

Power management

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TPS3430-Q1: What is the correct state of WDO# before SET1 is turned on during system power up?