BQ76930: Request the Design Review for BQ76930

Hi Louis,

Of course TIDA-01093 is our standard reference design for stacking 2 of the BQ769x0 devices, it seems you have followed that.  Schematic & BOM are provided along with some test data in the design guide.   In your schematic:

• The F41 circuit appears to duplicate the function of the F32 circuit.
• The Cc capacitors (C38, C39, C40...) are 1 uF like the TIDA-01093 and EVM.  With this value the settling time is long enough to see voltage artifacts when balancing.  Reducing the Cc value will avoid that, 0.22 uF and 0.1 uF have been used on other designs.
• See the application note http://www.ti.com/lit/pdf/slua749 section 10, particularly figure 21.  Some users have experienced damaged inputs.  With the smaller Cc capacitors the zener diodes may be more relevant.
• C48 and C49, the Cc capacitors for VC1 and VC0 are shown as 10 uF like C30 and C31 of the reference design.  The author did not describe the reason for these values or the schottky diodes on the nets.  As noted above the large value would show voltage errors due to long settling during balancing.  The Schottky diodes would prevent the pins from being pushed below VSS during heavy battery transients or loading.  You may want to select a more common type.  VC1 and VC0 similar to VC6 and VC5B have the lowest abs max of the cell inputs.  Zener diodes at the location of the Schottkys would limit the voltage if needed allowing a normal Cc value.