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Original question:

UCC28950: Secondary Synchronous Rectification under UCC28950 in Primary side

UCC28950: Gate Timing of Synchronous Rectification

Koshi Ninomiya
Expert 5435 points
Part Number: UCC28950
Other Parts Discussed in Thread: TINA-TI

Hi Team,

My customer is evaluating UCC28950 on their board. And there is a question about the adjustment method of switching timing of the synchronous rectification FET on the secondary side.
Please check an attached file.
UCC28950 Synchronous Rectification Gate Timing Adjustment.xlsx
They did TINA-TI simulation of "UCC28950 START-UP SIMULATION". Switching timing of the synchronous rectification FETs on the secondary side is normal.
But, when they operated it with their actual circuit, they found that VF1 was still High but there was a section where VF3 was High for about 80ns (same for the opposite Q5 side).
Please let me know if there is any adjustment method.

Is it sufficient to set the delay (increase the dead time) between the main switch FETs Q1 and Q4 (between Q2 and Q3) on the primary side of "UCC28950 START-UP SIMULATION"?
Thank you.

Best Regards,

Koshi Ninomiya

  • 0
    TI__Mastermind 25570 points

    Hello Ninomiya-san

    I'd suggest that the customer increase the tAFSET and tBESET delays. These are the delays between the primary switches (OUTA and OUTB) and the SRs (OUTF and OUTE). The adjustment can be done by increasing the value of the resistor at the DELEF pin. The resistor at the ADELEF pin also controls the delays by increasing them from the baseline delay set by R_DELEF in proportion to the current. The operation of the SR delays is described in the data sheet.

    The difference between the operation of the simulation and that of the real circuit is probably due to some additional propagation and switching delays in the physical components which are not modelled in the simulation.

    Regards

    Colin