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Hello,
I'm using your evaluation board LM5068EVAL (input voltage -12V) and I've put a pull-up resistor on PWRGD pin to a 5V external voltage:
- when the output voltage is not good the voltage on PWRGD is -10.4V;
- when the output voltage is good the voltage on PWRGD is 1.2V
why, if the internal circuit on PWRGD is a open-drain, the output voltage is not able to reach the pull-up voltage (5V)?
can you help me?
KR
Irene
Hi Irene,
Can you share me the schematic and pull-up resistor value ? Are you measuring with respect to VEE ? where is the return path of 5V external voltage connected ?
BR, Rakesh
Hi Irene,
It should be pulled to 5V level.
I have placed order for LM5068EVAL and will check as soon as I get it.
BR, Rakesh
Hi Rakesh,
please let me know as soon as possible because I have to freeze my schematic.
When you will have the evaluation board?
KR
Irene
Hi Irene,
I will receive EVM by 18th and will get back to you couple of days after that.
BR, Rakesh
Hi Irene,
I have received the EVM. I will check and let you know by tomorrow.
Can you share your full schematic.
BR, Rakesh
Hi Irene,
I have observed similar issue on EVM. Let me check with my team about the internal details of PWRGD and get back to you early next week.
Regards, Rakesh
Hi Irene,
The internal ESD diodes at the PWRGD (between PWRGD to VDD) is getting active because of the external 5V source leading to the voltages different than expected.
To overcome this, pull-up PWRGD to GND_Signal (as shown in datasheet) and then use external level shifter circuit. Let us know if you have follow up questions.
BR, Rakesh
Thank you Rakesh, have you tried a particular level shifter? Can you saggest me a part number?
thank you
Irene
Hi,
Where do you want to interface with the power good signal. ? Can you share your system block diagram and application use case details.
Is Figure-14 configuration in http://www.ti.com/lit/ds/symlink/tps23521.pdf work for you ?
Regards, Rakesh