TPS54824: Design Review

Hi Ranjana,

I have a few questions.

1. It looks like your attachment didn't come through. Can you try posting again?
2. Is the schematic in your previous post still valid for this design?
3. Is the increased output ripple when using the SSD as the load related to the load changing? Your two points make me think this is load transient related. If it is load transient related, adding the 47 pF capacitor in parallel with the upper feedback resistor suggested by Yuchang previously will help.
4. Do you have a requirement defined for the allowed min/max output voltage and the maximum load step size?

1. Please find the schematics(snapshot) attached. 

2. Please find the snapshot of the measurement (droop)

3. We used 47pF and 100pF  capacitor in parallel with upper feedback resistor, however could not see much improvement in the droop. 

Both the snapshots with 47pF and 100pF are as below:

with 47pF:

with 100pF:

Kindly let us know, how this droop related issue can be fixed. 

Regards,

Ranjana

Hi Ranjana,

The droop can almost definitely be reduced by increasing the loop bandwidth by increasing Rcomp (R22). Looking at the WEBENCH design the estimated loop bandwidth from the loop model there was 46 kHz. Closer to 90 kHz should be possible with 866kHz fsw. Try:

1. Increasing R22 by nearly 2x to 7.87kΩ.
2. With this increase in R22, it would also be beneficial to decrease C14 to 2.7 nF to keep the zero it provides near the same location as before and help with the settling time.
3. Also with the increase in R22, decrease the value of C15 by half to 68 pF to keep the the pole near the same location as before.

Do you have a specific target for the undershoot? The last waveform shows a little more than 5% undershoot. The changes I suggested above should decrease the undershoot almost in half.

Hi, 

Thanks for the above recommendations. 

In the design file earlier shared, we did the following changes: 

C17 = 100pf

R22 = 7.82 instead of 7.87kΩ.  No 7.87 available in our stock. 

 C14 = 2.7 nF

C15 = 68 pF

With these changes, the droop reduced.

However we would like to reduce this further, as we are planning to go in for larger quantity of units for build and would want to have as less droop as possible.

Kindly provide your suggestions on changes for further droop reduction.

Regards,

Ranjana 

Hi 

Can someone please provide the feedback for my earlier query.

Regards,

Ranjana

Hi Ranjana,

It can always be reduced further but may require more significant changes to the design, such as adding more output capacitance. If you would like to minimize changes to your design and only attempt to further optimize the compensation, you can use the TINA-TI average model linked below to optimize the compensation. Increasing R22 increases the loop bandwidth which reduces the undershoot. When increasing R22, you should decrease the series and parallel capacitor by a similar amount as I did in my previous recommendations.

When increasing R22, you still need to ensure sufficient phase and gain margin. I suggest ensuring at least 60 degrees phase margin and 15 dB gain margin.

TPS54824 TINA-TI Average Reference Design (Rev. C)

Do you have a target undershoot spec you are trying to meet? Right now the undershoot is around 3% and that is a normal amount of undershoot.