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Original question:

DRV103 Power-Pad tie to ground plane or isolate?

DRV103: Connecting ground to PowerPAD

Nathan C
Prodigy 200 points
Part Number: DRV103


The DRV103 datasheet says regarding the PowerPAD: "Do NOT use the exposed metal pad as a power ground connection or erratic operation will result."

My design utilizes the copper under the PowerPAD to connect adjacent DRV103 chips to ground, but it has a wide trace connecting directly to the GND pin (pin 4) on each DRV103. Is this a problem? I have not noticed any erratic behavior, but I am unsure exactly how to interpret the datasheet. It *could* mean that if I left the GND pin disconnected and tried to rely on just the PowerPAD for chip grounding, then erratic behavior would occur. This implies that as long as I provide a proper power ground connection to the GND pin of the DRV103, it's fine to also connect the PowerPAD to this ground (this is what I've done). But it could also mean I should leave the PowerPAD completely isolated.

I've attached an image of my layout showing how an amply-wide connection is made to the GND pin (pin 4):

Any advice here would be appreciated.

Thanks!

  • 0
    TI__Genius 13760 points

    Hi Nathan,

    Welcome to E2E!

    Your final interpretation would be the correct one. The ground pin of the device should be connected to the system ground, but the PowerPAD should be left isolated as this PowerPad is designed for the heat dissipation of the device.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 200 points

    Thanks for the clarification Andy. I've gone ahead and made an updated footprint to allow us to run a separate ground trace under the device. I notice that the datasheet says "Via pattern and copper pad size may vary depending on layout constraints". Do you have any feedback on the footprint below? Note that the distance between each row of vias has been reduced, and the thermal pad area is 57% of the example given in the datasheet. I increased the width of the solderpaste area so it remains the same (5.2mm^2) due to the decreased height of the pad.

    I don't expect this to have the same thermal characteristics as the example given in the datasheet, but if you notice anything strange or potentially problematic about the changes I made, I would like to know.

  • 0 in reply to Nathan C
    TI__Genius 13760 points

    Hi Nathan,

    I do not see any major concerns with your current footprint.

    For the thermal resistance refer to the package mounting portion in the datasheet that talks about the copper area that the PowerPad will be connected to.

    I also recommend taking a look into this document: PowerPad Made Easy, for extra information on the powerpad layout, including the via type that should be used for the PowerPad.

    Best regards,

    Andy Robles

  • 0 in reply to Andy Robles
    Prodigy 200 points

    Thanks for sending that reference over, Andy. I actually took a second look at the footprint and confirmed with a chip on hand that the exposed area on the bottom of the chip is only 2.28x2.28mm. Based on that knowledge, I limited the exposed copper on the PCB to approximately those dimensions. Now I'm getting about 75% of the original exposed heatsink coverage.