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Original question:

LMZM33606: Circuit only producing 11.36V when under load

LMZM33606: Board design for Inverting Buck Boost application

Spec Pro
Prodigy 120 points
Part Number: LMZM33606

Hi there,

Thanks for the help so far on the LMZM33606 I really appreciate the advice and support.

With regards to the IBB application of the LMZM33606 chip, the application notes don't include any suggestion for board layouts.  My project requires the design to generate three rails 12V, -12V and 5V from two LMZM33606.  My plan was to generate 12V from one chip and from that use a linear regulator to generate the 5V.  For the -12V I was planning to adapt the 12V design as follows (for Vin 15-20V, generating max 3A):

Questions I have are:

1) Are there any layout guidelines for the additional components of Cbulk, Cbyp, D1?  Or can I just follow the layout guidelines for the LMZM33606 and put these additional components anywhere?  Should the same LMZM33606 guidelines for board layers and planes be followed for the IBB?

2) For the PGND in the diagram, can I connect those to the same PGND as the LMZM33606 circuit generating the +12V?

3) Is the SYNC_Mode in the diagram the only item connected to the AGND?  Not sure if the black arrow means AGND or something else.

4) In Figure 1 of SNVA835B–July 2018–Revised May 2019, there is a SYS_GND in red.  Where do I connect that to in relation to the overall design?  Is it connected to the Vout plane that the +12V generating LMZM33606 is connected to?

5) All the power rails will come out of a 16 PIN connector.  Should the rails be connected to the PIN outs using circuits on the top most layer?

6) The schematic diagram above is missing a CFF capacitor.  Is a CFF required for the IBB application as per table 4 of SNVA835B (which shows values Cout = 435 uF and Cff = 100 pF)?

7) How much performance improvement in terms of lowering ripple and noise will be gained from clocking both LMZM33606 chips to the same clock?  Is it possible to use the same clock given one of them is inverting its output?

Many thanks again for the support!

  • 0
    TI__Guru 50120 points

    Hi Spec Pro,

    1. You can continue following the layout guidelines detailed in the LMZM33606 datasheet and make sure you are taking into consideration the IBB topology conversion.

    2. Yes this is the PGND of your input supply and could be used as reference for your positive (12V) output circuit.

    3. Note here that the module's AGND and PGND pin is designated as -VOUT for IBB topology and is the system reference. However the SYNC/MODE pin is connected to a "AGND symbol" which is higher than the module's system reference effectively putting the device in FPWM. If you wanted the device to operate in AUTO mode, you would connect the SYNC/MODE pin to the module's system reference. 

    4. The SYS_GND highlighted in the IBB topology for Figure 1 is connected to the system ground of your input supply (VIN) return.

    5. It is up to you how you fanout the output rails to your 16 pin connector. I'd pick whichever is easier to route without obstructing thermal relief and unbroken ground planes.

    6. It is not necessarily required to have a Cff. I'd suggest having the footprint on your PCB in the case you want to add it for additional stability. Notice in the SNVA835B app that the Cff was unpopulated for the system loop stability section (3.2).

    7. I have not exactly tested this so I don't have the numbers. But theoretically this will lower the interference between two different switching frequency. It will also make it easier to filter said noise in the case you want to tag on an input pi-filter. For the 5V application that uses a linear regulator, I'd image the PSRR characteristic of the regulator will be sufficient to lower ripple and noise on the 5V rail. I'd suggest testing this out on your end but I don't see how using the same clock for both inverting and non-inverting application would be an issue.

    Regards,

    Jimmy