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TPS53627: VID setpoint setting

Part Number: TPS53627
Other Parts Discussed in Thread: TPS53626,

Hi there,

I'm trying to evaluate TPS53626/7. I'm almost completing the schematic for a power rail (1.8V, Iccmax = 95A). From my understanding, several parameters can be set thru pin-strapping. However, in terms of Vout set point (VID), does it require Intel SVID debugging tool? Is it possible to set up the test board (power rail only) and evaluate the performance of these devices without Intel SVID debugging tool ?

  • Hello,

    The B-RAMP pin should have a voltage divider to VREF. 

    The lower resistor sets the RAMP setting per the datasheet. 

    The upper resistor generates a pin voltage on B-RAMP. The boot voltage will be 2x the voltage set point on B-RAMP by this divider. 

  • Hi, 

    Thank you for your answer. I understand what you explain on the thread above.

    One thing unclear for me, do you mean Vout equals to boot voltage? I brought the figure from Intel VRM datasheet, and my understanding from here is that VBOOT is not necessarily identical to VOUT. I've also seen the design examples where Vboot is not same as Vout. So can you help my understanding regarding this?

  • Hello,

    TPS53627 is an Intel VR13 SVID controller.  During normal operation the CPU may change the voltage using serial communication through the VDIO and VCLK pins.  This interface is specified by Intel and TI cannot share the documents directly due to NDA restrictions. At first power-on, the voltage will be initialized to the boot voltage given on the B-RAMP pin. After power-on, B-RAMP will be ignored, and the device will listen for SVID serial communication for new output voltage targets. 

    You should make sure the CPU you will attach to TPS53627 is made for VR13 SVID, or it will cause the CPU not to work . 

  • Hello Matt,

    Very clear! Thank you for your explanation.