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TPS53627: TPS53627 OCP level setting

MINKYUNG KIM
Expert 1250 points
Part Number: TPS53627

Hi e2e,

I'm reviewing the completed schematic before supporting customer on this device, trying to make this schematic as a reference. However I having difficulty setting the value for OCP level. Can you review the schematic below? 

OCP-I Pin is connected to 39.2kOhm and thereby V_CS(OCP) will be setting at 14 mV from the table in DS. For the next step, I follow several equations from DS to get Overcurrent Protection Current (I_OCP in the equations below). Equations on the left-hand side are equations from DS and the right-hand side is covered with my calculation.

I didn't share the full schematic here, but several design parameters are as below :

- 2 phases

- Icc(max) = 95 A, OCL = 55A

- DCR sensing : DCR value is 0.29 mOhm, which appears as R_CS(eff), 0.21 mOhm, with resistor dividing and DCR remote sensing circuit

As you can see the result, I_OCP is way out of the value that I targeted, 55A. Did I understand and solve the equations incorrect? Or is the schematic incorrectly designed? Please kindly clarify the OCP setting of this device. Will look forward to your answer. Thank you so much for your time and effort!

  • 0
    TI__Genius 11095 points

    Hello,

    (1) For Ipp please use your real inductor value.

    Ipp = [Vout * (Vin-Vout)] / [Vin * L * fsw)

    (2) Yes, this resistor will select Ivalley of ~67A

    (3) The OCL threshold here is per-phase. IOCP refers to the converter current which is why you get the 2x factor. 140A OCP vs 95A Iccmax is reasonable to me to give operating margin and prevent nuisance tripping. You can select a lower level by using the lower settings, or having bigger Rcs(eff) 

  • 0 in reply to Matt Schurmann
    Expert 1250 points

    Hello Matt,

    Understood. Thank you for your clear answer. Can I ask one more question?

    On the overall design process including OCP setting, I considered Icc(max) only. However there are two current specifications in Intel CPU, Icc(max) and Icc(TDC). (The attachments are referred from Intel VRM design guideline.) Could you give me some information about the actual operation of those currents and how those specifications get involved in the VRM design process? Thank you so much!

    Plus, this controller will be attached to the CPU that support VR13 SVID.

  • 0 in reply to MINKYUNG KIM
    TI__Genius 11095 points

    Hello, 

    The TDC current should be used to do the thermal design, including layer stackup, power loss, heat sinking, cooling etc... This represents effectively the average power of the CPU. Then based on whatever conversion efficiency you estimate, this will give the DC power loss your design should handle, at your max ambient temperature. 

    The peak current should be used to size your FET, inductor and OCP peak currents. The CPU current will jump up to the peak current periodically, but with low duty cycle. But it should be safe to operate the voltage regulator under these conditions. The Intel load transient specs will also be based on the IccMax value. 

  • 0 in reply to Matt Schurmann
    Expert 1250 points

    Hello,

    In terms of TDC and DC power loss you just mentioned, can the icc(TDC) be considered corresponding to 'Iout' from the usual buck converter? 

    To calculate efficiency of commonly-used buck converter, I should calculate losses, which include conduction loss (Iout*Iout*Rdson*D), switching loss (Vin*Iout*(t_rising+t_falling)*fsw/2) etc...

  • 0 in reply to MINKYUNG KIM
    TI__Genius 11095 points

    TDC current is for long duration, IccMax is peak current. 

    So, thermally the converter may be sized for ICCMAX DC power. But it still needs to operate at ICCMAX.