UCC28950: Simulation and datasheet

*$
* UCC28950
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* (C) Copyright 2019 Texas Instruments Incorporated. All rights reserved.                                            
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** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of 
** merchantability or fitness for a particular purpose.  The model is
** provided solely on an "as is" basis.  The entire risk as to its quality
** and performance is with the customer
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*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
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*
** Released by: Texas Instruments Inc.
* Part: UCC28950
* Date: 19JUL2019
* Model Type: TRANSIENT 
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: UCC28950EVM-442
* EVM Users Guide: SLUU421A�May 2010�Revised May 2010
* Datasheet: SLUSA16D �MARCH 2010�REVISED NOVEMBER 2016
* Topologies Supported: Buck
*
* Model Version: Final 1.2
*
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*
* Updates:
* 
* Final 1.2
* 
* 1. The following features have been are newly modeled or fixed.
*      a. Hiccup mode (Current Limit functionality).
*      b. Soft Start voltage pull up.
*      c. SYNC Pin fuctionality.
* 
* Final 1.10
* Updated model to fix Burst Mode
*
* Final 1.00
* Release to Web.
*
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*
* Model Usage Notes:
* 1. The following features have been modeled
*      a. MIN ON timer.
*      b. Voltge mode and Current mode.
*      c. Master and Slave mode. 
* 2. Temperature effects are not modeled. 
*
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.SUBCKT UCC28950_TRANS ADEL ADELEF COMP CS DCM DELAB DELCD DELEF EAM EAP GND OUTA
+  OUTB OUTC OUTD OUTE OUTF RSUM RT SSEN SYNC TMIN VDD VREF  
R_U4_R2         DCM U4_N134058  77K  
X_U4_U885         CLK U4_N138708 U4_N140048 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U4_U10          U4_N133974 U4_N134058 U4_N134506 COMPARATOR
C_U4_C2         0 U4_N134058  1.37p IC=0 
X_U4_U887         U4_N140048 U4_N924283 TMINP AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
G_U4_G3         0 U4_N138089 U4_TMIN_I 0 1
V_U4_V1         U4_N150346 0 2
X_U4_U18          U4_N144772 MS COMP_HYS2 PARAMS:  TH=1 HYS=1  T=10 
X_U4_U888         U4_N145738 U4_N134506 U4_N145189 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
C_U4_C3         U4_N133974 0  1.37p  
R_U4_R1         CS U4_N133974  77K  
X_U4_U889         U4_N134506 U4_N9250570 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U4_D1         U4_N132128 VREFBUF GEN_DIODE 
I_U4_I1         VREFBUF U4_N132128 DC 25u  
X_U4_U886         FAULT U4_N924283 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
G_U4_G2         U4_N144772 0 U4_N147222 0 0.1
X_U4_D4          U4_N144772 U4_N150346 DC_1mV_1A_1V_1nA
C_U4_C5         0 U4_N144772  1n IC=0 
E_U4_ABM1         U4_I_TMIN 0 VALUE { V(U4_TMIN_I)    }
X_U4_S7    CLK U4_N138089 DCMTMIN_U4_S7 
E_U4_ABM2         U4_N911725 0 VALUE {
+  (((V(VREFBUF)/V(U4_I_TMIN))/1000)*5.92)*0.000000001    }
X_U4_U891         MS U4_N152056 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U4_S6    U4_N152056 0 U4_N132128 DCM DCMTMIN_U4_S6 
X_U4_U883         U4_N138089 U4_V_TMIN U4_N138606 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
X_U4_U890         U4_N145738 U4_N9250570 U4_N147222 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U15         PWMN U4_N145738 ONE_SHOT PARAMS:  T=10  
X_U4_D2         U4_N138089 VREFBUF GEN_DIODE 
G_U4_G1         0 U4_N144772 U4_N145189 0 0.1
E_U4_ABM4         R_TMIN 0 VALUE { V(VREFBUF)/V(U4_TMIN_I)    }
X_U4_H1    VREFBUF TMIN U4_TMIN_I 0 DCMTMIN_U4_H1 
X_U4_U884         CLKN U4_N138606 U4_N138708 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U4_D5          0 U4_N144772 DC_1mV_1A_1V_1nA
E_U4_ABM3         U4_V_TMIN 0 VALUE { ( V(U4_I_TMIN)/11.84p)*V(U4_N911725)    
+  }
C_U4_C4         0 U4_N138089  11.84p IC=0 
X_U6_U2         PWM 0 U6_U1Q TRFF_RDOM 
X_U6_U26         QNB QA INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U28         U6_U1Q PWM TD XOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U6_U3         PWM 0 U6_N915416 TRFF_RDOM 
X_U6_U23         U6_U1Q U6_N911991 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U6_U25         C QNB QE OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U27         U6_N911991 PWM TC XOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U6_R1         U6_N915416 QNB  1  
X_U6_U24         D QA QNF OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U70         U2_SYNC_IN HICCUP_FAULT_BAR U2_N15287352 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U2_C1         0 U2_VOSC  1n IC=0 
V_U2_V1         U2_N919276 0 0.460
X_U2_U52         U2_N15268993 U2_SLAVE_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U68         U2_N15307604 U2_N15323663 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=1n
X_U2_U57         U2_N15287352 U2_N15289807 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_H1    U2_N47785 RT U2_SLAVE_IN 0 OSC_U2_H1 
X_U2_U72         HICCUP_FAULT_BAR U2_N15273433 U2_N15421955 AND2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U38         0 U2_TIME_PERIOD D_D1
R_U2_R6         0 U2_SYNC_IN  1e6  
X_U2_U23          U2_SLAVE_IN SLAVE COMPARATOR2 PARAMS:  TH=0  
E_U2_ABM1         U2_N15269089 0 VALUE { IF(V(U2_N15268959) > 0.5,1,0)    }
E_U2_ABM11         U2_N15268963 0 VALUE { IF(V(U2_SYNC_IN)>2.5,1,0)    }
X_U2_U69         U2_N15323663 U2_N15309112 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U33         U2_N14968918 U2_SYNC_IN U2_N14969162 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U36         U2_N14969162 U2_HICCUP_EN_OK U2_N14973647 N14974079
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U66         U2_N15309096 U2_N15309112 U2_N15309116 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U67         U2_N15309116 FAULT TIME_2ND N15316995 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U78         U2_SLAVE_B U2_N15432319 U2_N15274019 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
C_U2_C3         U2_TIME_PERIOD 0  1n IC=0 
E_U2_ABM6         U2_N15163724 0 VALUE {
+  if(V(U2_N14995361)>0,(2.5/(V(U2_N14995361))*4.815*21),0)    }
X_U2_S2    SLAVE 0 U2_SYNC_IN SYNC OSC_U2_S2 
X_U2_U55         U2_MASTER_CLK U2_N15260194 U2_N15274019 U2_N15273433
+  MUX2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U47         U2_N15010819 U2_N15045326 U2_N15038039 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U2_S5    U2_HICCUP_EN_OK 0 U2_TIME_PERIOD 0 OSC_U2_S5 
X_U2_U7         U2_N15268963 U2_N15268997 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U2_R1         U2_N103766 U2_MASTER_CLK  1  
X_U2_U59         U2_IIN_3RD U2_N15292373 U2_N15298392 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U74         TIME_2ND_B U2_SYNC_IN U2_N14996941 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
E_U2_ABM8         U2_N14951301 0 VALUE { (V(U2_SYNC_OUT) * 5)    }
X_U2_U37         U2_N14973647 U2_N14973789 U2_TIME_IN XOR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
R_U2_R5         U2_N15268997 U2_N15268973  3.16  
E_U2_ABM4         U2_SLAVE_IN_ABS 0 VALUE { ABS(V(U2_SLAVE_IN))    }
X_U2_U63         U2_IIN_3RD1 U2_SYNC_IN U2_N15307604 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_S3    U2_N15126732 0 SYNC U2_N14951301 OSC_U2_S3 
X_U2_U61         U2_N15296481 U2_IIN_3RD U2_N15298721 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U75         TIME_2ND TIME_2ND_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U2_R3         U2_N15160708 U2_N14995361  1  
X_U2_U76         U2_N15416974 0 U2_SLAVE_MODE N15418090 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U4         U2_SYNC_IN 0 U2_N14968918 TRFF_RDOM 
X_U2_U3         SLAVE U2_N15126732 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U27         0 U2_SLAVE_IN_ABS U2_N103766 U2_N102757 ANALOG_MUX 
V_U2_V4         U2_N47785 0 2.5
G_U2_G4         0 U2_TIME_PERIOD U2_TIME_IN 0 1
X_U2_U62         U2_N15298392 U2_N15298721 U2_IIN_3RD1 N15299389
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U40         U2_N15502782 U2_SYNC_IN U2_N15505395 AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U53         U2_N15268959 U2_N15268963 D_D1
C_U2_C7         U2_N15268973 0  1.43u IC=0 
V_U2_V3         U2_N15045326 0 1
X_U2_U60         U2_N15292373 U2_N15296481 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_S4    U2_N14996941 0 U2_N15010819 0 OSC_U2_S4 
X_U2_U73         U2_MASTER_CLK U2_N917872 U2_SYNC_OUT N919832
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U49         U2_N15038039 U2_N14996941 U2_SLAVE_CLK NOR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U26          U2_VOSC U2_MASTER_CLK COMP_HYS2 PARAMS:  TH=0.5 HYS=1  T=1
X_U2_S1    FAULT 0 U2_VOSC 0 OSC_U2_S1 
X_U2_U35         U2_N15502399 U2_N15502782 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U71         FAULT HICCUP_FAULT_BAR INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U54         U2_N15268973 U2_N15268997 D_D1
X_U2_U56         U2_N15287352 U2_N15289490 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=5n
X_U2_U31         U2_VOSC U2_N919276 U2_N917872 COMP_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5
C_U2_C5         U2_N14995361 0  1n IC=0 
E_U2_ABM2         U2_N15269215 0 VALUE { IF(V(U2_N15268973) > 0.5,1,0)    }
E_U2_ABM3         RAMP 0 VALUE { 2*V(U2_VOSC)    }
X_U2_U39         U2_N15505395 U2_HICCUP_EN_OK U2_N14973789 N15506170
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U2_C2         0 U2_N103766  1n IC=0 
X_U2_U5         CLK CLKN INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U6         U2_SYNC_IN 0 U2_N15502399 TRFF_RDOM 
G_U2_G5         0 U2_N15010819 U2_N15163724 0 1
X_U2_U77         U2_N15421955 U2_SLAVE_MODE CLK AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U2_U58         U2_N15289490 U2_N15289807 U2_IIN_3RD AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
G_U2_G3         U2_VOSC 0 U2_N102757 0 21
G_U2_G2         0 U2_VOSC U2_SLAVE_IN_ABS 0 1
X_U2_U9         U2_N15269089 U2_N15269215 U2_N15268993 OR2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
R_U2_R4         U2_N15268963 U2_N15268959  3.16  
E_U2_ABM9         U2_N15416974 0 VALUE { IF(V(SLAVE) > 0.5,V(U2_SYNC_IN),1)   
+  }
E_U2_ABM5         U2_N15160708 0 VALUE {
+  ((V(U2_TIME_PERIOD)*0.000000001*1000*1000*2.5*2.5*1000)*2)    }
X_U2_D1          0 U2_VOSC DC_1mV_1A_1V_1nA
E_U2_ABM10         U2_N15432319 0 VALUE { IF(V(SLAVE) > 0.5, V(TIME_2ND_B),0)  
+   }
E_U2_ABM7         U2_N15260194 0 VALUE {
+  IF(V(SLAVE)>0.5,V(U2_SLAVE_CLK),V(U2_MASTER_CLK))    }
C_U2_C4         U2_N15010819 0  1n IC=0 
C_U2_C6         U2_N15268959 0  1.43u IC=0 
X_U2_U64         U2_N15307604 U2_N15309096 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=5n
X_U2_U8         U2_IIN_3RD 0 U2_N15292373 TRFF_RDOM 
E_U8_ABM6         U8_N1227253 0 VALUE { V(VREFBUF)+V(U8_TCDSET_VIN)    }
R_U8_R1         U8_N113634 U8_N114050  5K  
G_U8_G3         0 U8_N1198281 U8_I_IN 0 1
X_U8_U13         U8_N128885 U8_N128881 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_D5         U8_N1227105 U8_N1227253 GEN_DIODE 
X_U8_D2         U8_N1198281 U8_N1211406 GEN_DIODE 
X_U8_U893         U8_N1265537 U8_RESC U8_N15348216 N1276268
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U8_S7    U8_N1262237 U8_N1227105 DELAYCD_U8_S7 
X_U8_U887         TD BFAULT_SHIFT_C U8_N1019891 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
R_U8_R2         0 U8_N114050  2Meg  
X_U8_U907         U8_N15350041 HICCUP_FAULT_BAR D AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_U892         U8_N1255156 U8_RESD U8_N15350041 N1227407
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U8_ABM8         U8_RES 0 VALUE { IF(V(SLAVE) >0.5,V(TIME_2ND),1)    }
E_U8_ABM7         U8_K 0 VALUE { IF(V(ADEL)>0,1,0)    }
X_U8_U901         PWM U8_RESD U8_N1262237 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U899         U8_N1227105 U8_TCDSET_VIN U8_N1255156 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U8_U885         BFAULT_SHIFT_C U8_N1170281 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U896         U8_N1198281 U8_TCDSET_VIN U8_N1265537 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U8_S4    U8_N128885 0 VDD OUTD DELAYCD_U8_S4 
X_U8_U912         C U8_RES U8_N1170281 U8_N128685 AND3_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_S6    U8_N1242981 U8_N1198281 DELAYCD_U8_S6 
G_U8_G4         0 U8_N1227105 U8_I_IN 0 1
X_U8_S5    U8_N128881 0 OUTD 0 DELAYCD_U8_S5 
X_U8_S2    U8_N128685 0 VDD OUTC DELAYCD_U8_S2 
C_U8_C2         0 U8_N114050  40p  
E_U8_ABM5         U8_N1211406 0 VALUE { V(VREFBUF)+V(U8_TCDSET_VIN)    }
X_U8_U913         D U8_RES U8_N963700 U8_N128885 AND3_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_U891         U8_RESC PWM U8_N1242981 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_D4         0 U8_N1227105 GEN_DIODE 
C_U8_C3         0 U8_N1198281  1.77p IC=0 
X_U8_H1    U8_V_IN DELCD U8_I_IN 0 DELAYCD_U8_H1 
X_U8_U20         U8_N1018897 U8_RESD BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
X_U8_S3    U8_N128681 0 OUTC 0 DELAYCD_U8_S3 
G_U8_G1         ADEL U8_N113634 TABLE { V(ADEL, U8_N113634) } 
+ ( (-5,0) (0,1n)(0.01,1u)(0.1,1) )
X_U8_U886         TC BFAULT_SHIFT_C U8_N1018897 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U8_U12         U8_N128685 U8_N128681 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U8_U21         U8_N1019891 U8_RESC BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
E_U8_ABM2         U8_R_IN 0 VALUE { (V(U8_V_IN)/V(U8_I_IN))/1000    }
X_U8_U906         U8_N15348216 HICCUP_FAULT_BAR C AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
V_U8_V2         U8_V_IN U8_N112342 0.210
X_U8_D3         0 U8_N1198281 GEN_DIODE 
C_U8_C4         0 U8_N1227105  1.77p IC=0 
X_U8_U17         BFAULT_SHIFT_C U8_N963700 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U8_ABM3         U8_TCDSET_VIN 0 VALUE {
+  (((5*V(U8_R_IN))/(0.26+LIMIT(V(CS),0,1.8)*1.3*V(U8_K)))*0.000000001*V(U8_I_IN))/(1.77*0.000000000001)
+     }
E_U8_ABM1         U8_N112342 0 VALUE { LIMIT(V(U8_N114050) * 10,0.02,4.25)    }
X_U3_U28          U3_PWM_H U3_PWM_L INVERTER
G_U3_G2         U3_N854877 COMP TABLE { V(U3_N854877, COMP) } 
+ ( (-10,-5m)(-1m,-4.6m) (1m,3.75m)(10,4.5m) )
X_U3_U33         PWMI U3_N15171995 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=100n
X_U3_H1    VRM2R5V RSUM U3_N111703 0 EAPWM_U3_H1 
X_U3_D1         U3_ME VREFBUF GEN_DIODE 
X_U3_U25         RAMP U3_N115946 U3_PCM U3_N1119181 ANALOG_MUX
X_U3_U24          COMP U3_N112167 U3_PWM_H COMPARATOR
X_U3_U31         U3_PWM_L CLK PWMI RSFF_RDOM_VAR PARAMS:  T=10 
X_U3_U21         U3_N110746 EAM U3_N854877 OP_AMP PARAMS:  HLIMIT=4.25 RIN=1MEG
+  BW=3MEG DC_GAIN=100 ROUT=100 LLIMIT=0.25 SRP=1   SRM=1 
E_U3_ABM4         U3_N113332 0 VALUE { ABS(V(U3_N111703))*2    }
G_U3_G1         GND U3_ME U3_N113332 0 0.001
X_U3_U23          U3_N111703 U3_PCM COMPARATOR2 PARAMS:  TH=0  
V_U3_V1         U3_N112167 U3_N1119181 0.85
C_U3_C2         U3_N854877 COMP  10p IC=0 
C_U3_C1         U3_ME 0  1n IC=0 
X_U3_S3    FAULT_1 CS EAPWM_U3_S3 
X_U3_U35         PWMI U3_N15175139 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U3_U27          U3_N115946 OC COMPARATOR2 PARAMS:  TH=2  
E_U3_ABM3         U3_N110746 0 VALUE { if(V(EAP)<V(REFSS),V(EAP),V(REFSS))  
+     }
X_U3_S1    FAULT_1 COMP EAPWM_U3_S1 
X_U3_S2    CLK U3_ME EAPWM_U3_S2 
X_U3_U26          U3_ME CS U3_N115946 ANALOG_SUMMER 
X_U3_U34         U3_N15171995 U3_N15175139 U3_CS_S_R AND2_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
R_R1         0 GND  1m  
X_U11         PWM N15201465 INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
+  DELAY=20n
X_S1    N15201465 0 CS 0 UCC28950_S1 
X_U9_U18         U9_N128783 U9_N128881 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U9_R1         U9_N113634 U9_N114050  5K  
X_U9_U22         FAULT U9_N935984 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U9_U26         U9_FDEL U9_N938984 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
G_U9_G2         0 U9_N115562 U9_I_IN 0 1
X_U9_U895         U9_N122413 U9_N143329 U9_EDEL N1186789 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U9_U27         U9_N138558 U9_N938984 U9_N1193704 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U9_U894         U9_N122413 U9_N1020124 U9_FDEL N1030889 SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U9_ABM4         U9_N998652 0 VALUE { V(VREFBUF)+V(U9_TFESET_VIN)    }
X_U9_U29         QNF U9_N1020124 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
X_U9_U16         U9_N121368 CLK U9_N122413 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U9_S1    CLK U9_N115562 DELAYEF_U9_S1 
X_U9_U19         FAULT U9_FAULT_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U9_R2         0 U9_N114050  2Meg  
X_U9_U892         U9_N1192437 U9_FAULT_B U9_E AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U9_U25         U9_N138558 U9_N938419 U9_N1192437 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U9_U11         U9_N115562 U9_TFESET_VIN U9_N987398 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U9_D1         U9_N115562 U9_N998652 GEN_DIODE
X_U9_S4    U9_N128783 0 VDD OUTE DELAYEF_U9_S4 
X_U9_H1    U9_V_IN DELEF U9_I_IN 0 DELAYEF_U9_H1 
X_U9_U20         U9_F U9_FAULT_B U9_N128579 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U9_S5    U9_N128881 0 OUTE 0 DELAYEF_U9_S5 
X_U9_S2    U9_N128579 0 VDD OUTF DELAYEF_U9_S2 
X_U9_U17         U9_N128579 U9_N128681 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U9_C2         0 U9_N114050  40p  
X_U9_U21         U9_E U9_N935984 U9_N128783 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U9_U893         U9_N1193704 U9_FAULT_B U9_F AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
E_U9_ABM1         U9_N112342 0 VALUE { LIMIT(V(U9_N114050) * 10,0.02,4.25)    }
X_U9_U23         MS BURST U9_N138558 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U9_ABM6         U9_K 0 VALUE { IF(V(ADELEF)>0,1,0)    }
X_U9_S3    U9_N128681 0 OUTF 0 DELAYEF_U9_S3 
E_U9_ABM2         U9_R_IN 0 VALUE { (V(U9_V_IN)/V(U9_I_IN))/1000    }
G_U9_G1         ADELEF U9_N113634 TABLE { V(ADELEF, U9_N113634) } 
+ ( (-5,0) (0,1n)(0.01,1u)(0.1,1) )
X_U9_U28         QE U9_N143329 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
X_U9_U24         U9_EDEL U9_N938419 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
C_U9_C1         0 U9_N115562  1.915p IC=0 
V_U9_V2         U9_V_IN U9_N112342 2.48
E_U9_ABM3         U9_TFESET_VIN 0 VALUE {
+  (((((5*V(U9_R_IN))/(2.65-LIMIT(V(CS),0,1.8)*1.32*V(U9_K)))*0.000000001)+4*1n)*V(U9_I_IN))/(1.915*1p)
+     }
X_U9_U15         U9_N987398 CLKN U9_N121368 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_S1    CLK U7_N115562 DELAYAB_U7_S1 
X_U7_U868         BFAULT_SHIFT U7_N1052118 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U871         A U7_N1141763 U7_N1057855 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U894         QA U7_RES U7_N15488899 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U892         U7_N1128713 U7_N1128833 U7_N1128837 N1171824
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
G_U7_G1         ADEL U7_N113634 TABLE { V(ADEL, U7_N113634) } 
+ ( (-5,0) (0,1n)(0.01,1u)(0.1,1) )
X_U7_U870         U7_N1057855 U7_N1065753 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U890         U7_N1128837 HICCUP_FAULT_BAR B AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
R_U7_R2         0 U7_N114050  2Meg  
X_U7_U20         U7_N15488899 U7_N1128833 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=10n
E_U7_ABM4         U7_N999252 0 VALUE { V(VREFBUF)+V(U7_TABSET_VIN)    }
E_U7_ABM5         U7_K 0 VALUE { IF(V(ADEL)>0,1,0)    }
X_U7_D1         U7_N115562 U7_N999252 GEN_DIODE 
X_U7_U885         BFAULT_SHIFT U7_N1141763 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U11         U7_N115562 U7_TABSET_VIN U7_N1084353 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U7_U867         B U7_N1052118 U7_N127334 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_U893         U7_N1128713 U7_N1128749 U7_N1128851 N1172589
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U7_U21         U7_N15503737 U7_N1128749 BUF_DELAY_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=10n
X_U7_U895         QNB U7_RES U7_N15503737 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
V_U7_V2         U7_V_IN U7_N112342 0.210
X_U7_S4    U7_N127334 0 VDD OUTB DELAYAB_U7_S4 
X_U7_S2    U7_N1057855 0 VDD OUTA DELAYAB_U7_S2 
E_U7_ABM2         U7_R_IN 0 VALUE { (V(U7_V_IN)/V(U7_I_IN))/1000    }
E_U7_ABM6         U7_RES 0 VALUE { IF(V(SLAVE) >0.5,V(TIME_2ND_B),0)    }
X_U7_S5    U7_N127436 0 OUTB 0 DELAYAB_U7_S5 
E_U7_ABM3         U7_TABSET_VIN 0 VALUE {
+  (((5*V(U7_R_IN))/(0.26+LIMIT(V(CS),0,1.8)*1.3*V(U7_K)))*0.000000001*V(U7_I_IN))/(1.77*0.000000000001)
+     }
X_U7_U14         U7_N127334 U7_N127436 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U7_S3    U7_N1065753 0 OUTA 0 DELAYAB_U7_S3 
X_U7_U876         U7_N1084353 CLKN U7_N1126723 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
G_U7_G2         0 U7_N115562 U7_I_IN 0 1
C_U7_C1         0 U7_N115562  1.77p IC=0 
C_U7_C2         0 U7_N114050  40p  
X_U7_U891         U7_N1128851 HICCUP_FAULT_BAR A AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U7_H1    U7_V_IN DELAB U7_I_IN 0 DELAYAB_U7_H1 
X_U7_U881         U7_N1126723 CLK U7_N1128713 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U7_R1         U7_N113634 U7_N114050  5K  
E_U7_ABM1         U7_N112342 0 VALUE { LIMIT(V(U7_N114050) * 10,0.02,4.25)    }
X_U1_U26          VREF U1_N107412 COMPARATOR2 PARAMS:  TH=4.9
X_U1_U890         U1_HICCUP_TIMEOUT U1_N16796815 BUF_DELAY_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=1n
E_U1_ABM13         U1_N16803614 0 VALUE { IF( V(U1_SSEND)>0.5,V(CS),0 )    }
E_U1_ABM7         U1_N16780645 0 VALUE { if(V(SLAVE)>0.5,25u,20u)    }
X_U1_U893         U1_HICCUP_EN_START U1_HICCUP_EN U1_HICCUP_TOTAL OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U1_U25          U1_5V U1_1V ANALOG_BUFFER PARAMS:  GAIN=0.2 
E_U1_ABM3         U1_FAST_PULL_UP_I 0 VALUE {
+  if(V(U1_HICCUP_EN)<0.5,if(V(SSEN)>3.6,1,0),0)    }
X_U1_U24          U1_5V U1_N112197 ANALOG_BUFFER PARAMS:  GAIN=0.93 
V_U1_V16         U1_N868574 0 1
R_U1_R2         0 U1_TRIP  100MEG  
C_U1_C2         0 FAULT  1n  
G_U1_ABM2I1         SSEN 0 VALUE { IF(V(U1_HICCUP_EN) >0.5,V(U1_N16780645),0)  
+    }
E_U1_ABM10         U1_N16790700 0 VALUE { IF(V(U1_N16816339)<3.6,0,1)    }
X_U1_U898         U1_HICCUP_EN_OK_B U1_N107412 U1_N106282 U1_N107478
+  U1_N16879479 NAND4_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U1_V28         U1_N16794656 0 1
R_U1_R1         U1_N105859 U1_5V  1  
E_U1_ABM14         U1_N16816339 0 VALUE { IF(V(U1_HICCUP_EN)>0.5,V(SSEN),4)   
+  }
V_U1_V30         U1_N16827506 0 4.66
X_U1_U888         U1_N16790700 U1_HICCUP_EN_START INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U1_U683         U1_HICCUP_TIMEOUT N16796320 U1_N16819644 U1_N16794656
+  U1_N16796815 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U1_S1    U1_TRIP 0 CS 0 HK_U1_S1 
X_U1_U895         U1_HICCUP_EN U1_FAST_PULL_UP_I U1_N16835002 OR2_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U1_U14          U1_N106282 U1_N105859 ANALOG_BUFFER PARAMS:  GAIN=5 
G_U1_ABMII1         GND SSEN VALUE { IF(V(U1_N16835002) > 0.5, 0, 25u)    }
V_U1_V27         U1_N872720 0 2
R_U1_R3         U1_N16879479 FAULT  1  
X_U1_U900         U1_N107412 U1_N106282 U1_N107478 FAULT_1 NOR3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U1_U892         U1_N16820625 U1_N16819294 U1_N16819644 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
E_U1_LIMIT1         REFSS 0 VALUE {LIMIT(V(U1_N112871),0,5)}
E_U1_ABM11         U1_N16819294 0 VALUE { IF(V(U1_HICCUP_TOTAL)>0.5,V(SSEN),0) 
+    }
X_U1_U891         U1_N868408 U1_HICCUP_TIMEOUT U1_HICCUP_EN N16807368
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U1_ABM2         VRM2R5V 0 VALUE {
+  if(V(VREF)-V(U1_N108451)<0,0,V(VREF)-V(U1_N108451))  
+     }
X_U1_U899         HICCUP_EN_OK U1_HICCUP_EN_OK_B INV_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U1_U17          VDD U1_N106282 COMP_HYS2 PARAMS:  TH=7 HYS=0.6  T=50 
X_U1_D1          SSEN U1_N112197 DC_1mV_1A_1V_1nA
E_U1_ABM15         U1_SSEND 0 VALUE { if(V(SSEN) >4.6,1,0)    }
E_U1_ABM8         U1_N16786800 0 VALUE { if(V(SLAVE)>0.5,-22.5u,-17.5u)    }
G_U1_ABM2I2         SSEN 0 VALUE { IF(V(HICCUP_EN_OK) >0.5,V(U1_N16786800),0)  
+    }
X_U1_U19          SSEN U1_N107478 COMP_HYS2 PARAMS:  TH=0.525 HYS=0.05  T=50
X_U1_U16          U1_5V U1_N108451 ANALOG_BUFFER PARAMS:  GAIN=0.5 
V_U1_V29         U1_N16820625 0 0.55
X_U1_U887         U1_N16803614 U1_N872720 U1_N868408 COMP_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U1_S2    U1_FAST_PULL_UP_I 0 U1_N16827506 SSEN HK_U1_S2 
V_U1_V1         SSEN U1_N112871 0.55
X_U1_U15         U1_5V VREF ILIMIT PARAMS:  IP=23m   IM=1m   VHARD=100   
X_U1_U681         HICCUP_EN_OK U1_HICCUP_EN_OK_BAR U1_HICCUP_EN_START
+  U1_N868574 U1_HICCUP_TIMEOUT 0 DFFSR_RHPBASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U1_U22          VREF VREFBUF ANALOG_BUFFER PARAMS:  GAIN=1 
C_U1_C1         U1_5V 0  1n IC=5 
X_U1_U894         U1_N868408 U1_TRIP BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=10n
X_U5_U34         TMINP PWMI U5_N201516 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U55         U5_N253241 U5_N253069 U5_N253391 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U35         TMINP U5_N218486 U5_N201669 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U32         PWM PWMN INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U22         U5_N147631 U5_N146148 U5_N202297 RSFF_RDOM_VAR PARAMS:  T=10 
X_U5_U20         U5_N144968 U5_N144019 U5_N153858 RSFF_RDOM_VAR PARAMS:  T=10 
X_U5_U18         U5_N240684 0 U5_N240492 TRFF_RDOM 
X_U5_U16         U5_N141258 0 U5_BSYNC TRFF_RDOM 
X_U5_U30         U5_N253103 0 U5_N253069 TRFF_RDOM 
X_U5_U56         U5_N253391 BURST BFAULT_SHIFT_C NOR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U52         U5_N240730 U5_N240452 U5_N243856 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U38         U5_N155915 U5_N156103 PWM AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U23         U5_N240452 0 U5_N240730 TRFF_RDOM 
R_U5_R3         U5_N202297 0  1k  
X_U5_U28         U5_N165574 0 U5_N141258 TRFF_RDOM 
X_U5_U49         BURST PWMI CLKN U5_N151959 AND3_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U42         U5_N145999 U5_BSYNC U5_N146148 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U44         U5_N145999 U5_N147313 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U46         U5_BSYNC U5_N141258 U5_N141346 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U24         CLKN 0 U5_N253195 TRFF_RDOM 
X_U5_U14         CLK 0 U5_N140448 TRFF_RDOM 
X_U5_U25         U5_N253195 0 U5_N253103 TRFF_RDOM 
X_U5_U36         PWMI U5_N218486 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U48         TMINP U5_N227196 U5_N142322 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U40         U5_N253069 0 U5_N253241 TRFF_RDOM 
X_U5_U33         BURST BURSTN INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U51         U5_N141346 BURST U5_N190650 NOR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
R_U5_R1         U5_BSYNC 0  1k  
X_U5_U37         U5_N190650 FAULT BFAULT OR2_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U15         U5_N140448 0 U5_N165574 TRFF_RDOM 
R_U5_R2         BURST 0  1k  
X_U5_U47         FAULT U5_N227196 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U27         OC CLK U5_N156103 RSFF_RDOM_VAR PARAMS:  T=10 
X_U5_U54         CLK U5_N246945 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U5_U26         U5_N153858 U5_N145999 DELAY PARAMS:  T=200  
X_U5_U43         U5_N147313 U5_BSYNC U5_N147631 AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U45         U5_N141346 U5_N142322 U5_TMINC AND2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U53         U5_N243856 BURST BFAULT_SHIFT NOR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U29         U5_N240492 0 U5_N240452 TRFF_RDOM 
X_U5_U19         U5_TMINC PWMI U5_N144019 RSFF_RDOM_VAR PARAMS:  T=10 
R_U5_R5         U5_N253241 0  1k  
X_U5_U31         U5_N201669 U5_N201516 BURST RSFF_RDOM_VAR PARAMS:  T=10 
X_U5_U50         TMINP U5_TMINC CLKN BURSTN U5_N151882 AND4_BASIC_GEN PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U21         PWMI U5_TMINC U5_N144968 RSFF_RDOM_VAR PARAMS:  T=10 
R_U5_R4         U5_N240730 0  1k  
X_U5_U39         U5_N151959 U5_N151882 U5_N155915 OR2_BASIC_GEN PARAMS: VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U17         U5_N246945 0 U5_N240684 TRFF_RDOM 
.ENDS UCC28950_TRANS
*$
.subckt DCMTMIN_U4_S7 1 3  
S_U4_S7         3 0 1 0 _U4_S7
RS_U4_S7         1 0 1G
.MODEL         _U4_S7 VSWITCH Roff=100e6 Ron=1.0 Voff=0.25V Von=0.75V
.ends DCMTMIN_U4_S7
*$
.subckt DCMTMIN_U4_S6 1 2 3 4  
S_U4_S6         3 4 1 2 _U4_S6
RS_U4_S6         1 2 1G
.MODEL         _U4_S6 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25V Von=0.75V
.ends DCMTMIN_U4_S6
*$
.subckt DCMTMIN_U4_H1 1 2 3 4  
H_U4_H1         3 4 VH_U4_H1 1
VH_U4_H1         1 2 0V
.ends DCMTMIN_U4_H1
*$
.subckt OSC_U2_H1 1 2 3 4  
H_U2_H1         3 4 VH_U2_H1 4.815
VH_U2_H1         1 2 0V
.ends OSC_U2_H1
*$
.subckt OSC_U2_S2 1 2 3 4  
S_U2_S2         3 4 1 2 _U2_S2
RS_U2_S2         1 2 1G
.MODEL         _U2_S2 VSWITCH Roff=10e9 Ron=1 Voff=0.25V Von=0.75V
.ends OSC_U2_S2
*$
.subckt OSC_U2_S5 1 2 3 4  
S_U2_S5         3 4 1 2 _U2_S5
RS_U2_S5         1 2 1G
.MODEL         _U2_S5 VSWITCH Roff=1e9 Ron=1m Voff=0.25V Von=0.75V
.ends OSC_U2_S5
*$
.subckt OSC_U2_S3 1 2 3 4  
S_U2_S3         3 4 1 2 _U2_S3
RS_U2_S3         1 2 1G
.MODEL         _U2_S3 VSWITCH Roff=10e9 Ron=1 Voff=0.25V Von=0.75V
.ends OSC_U2_S3
*$
.subckt OSC_U2_S4 1 2 3 4  
S_U2_S4         3 4 1 2 _U2_S4
RS_U2_S4         1 2 1G
.MODEL         _U2_S4 VSWITCH Roff=100e6 Ron=1.0 Voff=0.2V Von=0.8V
.ends OSC_U2_S4
*$
.subckt OSC_U2_S1 1 2 3 4  
S_U2_S1         3 4 1 2 _U2_S1
RS_U2_S1         1 2 1G
.MODEL         _U2_S1 VSWITCH Roff=1e9 Ron=1m Voff=0.25V Von=0.75V
.ends OSC_U2_S1
*$
.subckt DELAYCD_U8_S7 1 3  
S_U8_S7         3 0 1 0 _U8_S7
RS_U8_S7         1 0 1G
.MODEL         _U8_S7 VSWITCH Roff=1e9 Ron=0.1 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S7
*$
.subckt DELAYCD_U8_S4 1 2 3 4  
S_U8_S4         3 4 1 2 _U8_S4
RS_U8_S4         1 2 1G
.MODEL         _U8_S4 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S4
*$
.subckt DELAYCD_U8_S6 1 3  
S_U8_S6         3 0 1 0 _U8_S6
RS_U8_S6         1 0 1G
.MODEL         _U8_S6 VSWITCH Roff=1e9 Ron=0.1 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S6
*$
.subckt DELAYCD_U8_S5 1 2 3 4  
S_U8_S5         3 4 1 2 _U8_S5
RS_U8_S5         1 2 1G
.MODEL         _U8_S5 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S5
*$
.subckt DELAYCD_U8_S2 1 2 3 4  
S_U8_S2         3 4 1 2 _U8_S2
RS_U8_S2         1 2 1G
.MODEL         _U8_S2 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S2
*$
.subckt DELAYCD_U8_H1 1 2 3 4  
H_U8_H1         3 4 VH_U8_H1 1
VH_U8_H1         1 2 0V
.ends DELAYCD_U8_H1
*$
.subckt DELAYCD_U8_S3 1 2 3 4  
S_U8_S3         3 4 1 2 _U8_S3
RS_U8_S3         1 2 1G
.MODEL         _U8_S3 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYCD_U8_S3
*$
.subckt EAPWM_U3_H1 1 2 3 4  
H_U3_H1         3 4 VH_U3_H1 1000
VH_U3_H1         1 2 0V
.ends EAPWM_U3_H1
*$
.subckt EAPWM_U3_S3 1 3  
S_U3_S3         3 0 1 0 _U3_S3
RS_U3_S3         1 0 1G
.MODEL         _U3_S3 VSWITCH Roff=100e6 Ron=1.0 Voff=0.25V Von=0.75V
.ends EAPWM_U3_S3
*$
.subckt EAPWM_U3_S1 1 3  
S_U3_S1         3 0 1 0 _U3_S1
RS_U3_S1         1 0 1G
.MODEL         _U3_S1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.25V Von=0.75V
.ends EAPWM_U3_S1
*$
.subckt EAPWM_U3_S2 1 3  
S_U3_S2         3 0 1 0 _U3_S2
RS_U3_S2         1 0 1G
.MODEL         _U3_S2 VSWITCH Roff=1e9 Ron=1.0 Voff=0.25V Von=0.75V
.ends EAPWM_U3_S2
*$
.subckt UCC28950_S1 1 2 3 4  
S_S1         3 4 1 2 _S1
RS_S1         1 2 1G
.MODEL         _S1 VSWITCH Roff=1000e6 Ron=200 Voff=0.2V Von=0.75V
.ends UCC28950_S1
*$
.subckt DELAYEF_U9_S1 1 3  
S_U9_S1         3 0 1 0 _U9_S1
RS_U9_S1         1 0 1G
.MODEL         _U9_S1 VSWITCH Roff=1e9 Ron=0.1 Voff=0.25V Von=0.75V
.ends DELAYEF_U9_S1
*$
.subckt DELAYEF_U9_S4 1 2 3 4  
S_U9_S4         3 4 1 2 _U9_S4
RS_U9_S4         1 2 1G
.MODEL         _U9_S4 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYEF_U9_S4
*$
.subckt DELAYEF_U9_H1 1 2 3 4  
H_U9_H1         3 4 VH_U9_H1 1
VH_U9_H1         1 2 0V
.ends DELAYEF_U9_H1
*$
.subckt DELAYEF_U9_S5 1 2 3 4  
S_U9_S5         3 4 1 2 _U9_S5
RS_U9_S5         1 2 1G
.MODEL         _U9_S5 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYEF_U9_S5
*$
.subckt DELAYEF_U9_S2 1 2 3 4  
S_U9_S2         3 4 1 2 _U9_S2
RS_U9_S2         1 2 1G
.MODEL         _U9_S2 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYEF_U9_S2
*$
.subckt DELAYEF_U9_S3 1 2 3 4  
S_U9_S3         3 4 1 2 _U9_S3
RS_U9_S3         1 2 1G
.MODEL         _U9_S3 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYEF_U9_S3
*$
.subckt DELAYAB_U7_S1 1 3  
S_U7_S1         3 0 1 0 _U7_S1
RS_U7_S1         1 0 1G
.MODEL         _U7_S1 VSWITCH Roff=1e9 Ron=0.1 Voff=0.25V Von=0.75V
.ends DELAYAB_U7_S1
*$
.subckt DELAYAB_U7_S4 1 2 3 4  
S_U7_S4         3 4 1 2 _U7_S4
RS_U7_S4         1 2 1G
.MODEL         _U7_S4 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYAB_U7_S4
*$
.subckt DELAYAB_U7_S2 1 2 3 4  
S_U7_S2         3 4 1 2 _U7_S2
RS_U7_S2         1 2 1G
.MODEL         _U7_S2 VSWITCH Roff=1e6 Ron=20 Voff=0.25V Von=0.75V
.ends DELAYAB_U7_S2
*$
.subckt DELAYAB_U7_S5 1 2 3 4  
S_U7_S5         3 4 1 2 _U7_S5
RS_U7_S5         1 2 1G
.MODEL         _U7_S5 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYAB_U7_S5
*$
.subckt DELAYAB_U7_S3 1 2 3 4  
S_U7_S3         3 4 1 2 _U7_S3
RS_U7_S3         1 2 1G
.MODEL         _U7_S3 VSWITCH Roff=1e6 Ron=10 Voff=0.25V Von=0.75V
.ends DELAYAB_U7_S3
*$
.subckt DELAYAB_U7_H1 1 2 3 4  
H_U7_H1         3 4 VH_U7_H1 1
VH_U7_H1         1 2 0V
.ends DELAYAB_U7_H1
*$
.subckt HK_U1_S1 1 2 3 4  
S_U1_S1         3 4 1 2 _U1_S1
RS_U1_S1         1 2 1G
.MODEL         _U1_S1 VSWITCH Roff=1000MEG Ron=200 Voff=0.25V Von=0.75V
.ends HK_U1_S1
*$
.subckt HK_U1_S2 1 2 3 4  
S_U1_S2         3 4 1 2 _U1_S2
RS_U1_S2         1 2 1G
.MODEL         _U1_S2 VSWITCH Roff=100e9 Ron=1k Voff=0.25V Von=0.75V
.ends HK_U1_S2
*$
.SUBCKT AND A B OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 & V(B)>0.5,1,0) }
.ends AND
*$
.SUBCKT AND_1 A B OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 & V(B)<0.5,1,0) }
.ends AND_1
*$
.SUBCKT INVERTER IN OUT  
EOUT OUT 0 VALUE { IF( V(IN)<0.5,1,0) }
.ends INVERTER
*$
.SUBCKT NAND3 A B C OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 & V(B)>0.5 & V(C)>0.5,0,1) }
.ends NAND3
*$
.SUBCKT NOR A B OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 | V(B)>0.5,0,1) }
.ends NOR
*$
.SUBCKT ONE_SHOT IN OUT
+ PARAMs:  T=100
S_S1         MEAS 0 RESET2 0 S1
E_ABM1         CH 0 VALUE { if( V(IN)>0.5 | V(OUT)>0.5,1,0)    }
R_R2         RESET2 RESET  0.1  
E_ABM3         OUT 0 VALUE { if( V(MEAS)<0.5 & V(CH)>0.5,1,0)    }
R_R1         MEAS CH  {T} 
C_C2         0 RESET2  1.4427n  
C_C1         0 MEAS  1.4427n  
E_ABM2         RESET 0 VALUE { if(V(CH)<0.5,1,0)    }
.MODEL         S1 VSWITCH Roff=1e9 Ron=1.0 Voff=0.25V Von=0.75V
.ENDS ONE_SHOT
*$
.SUBCKT UCCX7324 VINA GND VINB VOUTB VDD VOUTA
R1 4 GND 1
R2 VDD 2 30
D2 VDD 2 _D2_MOD1
.MODEL _D2_MOD1 D IS=1F N=1 RS=1.9
D3 2 VDD _D3_MODX
.MODEL _D3_MODX D BV=3.2 IBV=.1 N=.1 RS=.39
D1 GND 4 _DZ
.MODEL _DZ D BV=1.61 IBV=.1 N=.1 RS=.11
M1 2 3 VOUTA VOUTA _MTOP
.MODEL _MTOP NMOS KP=10 LAMBDA=1M VTO=4.1
M2 4 3 VOUTA VOUTA _PMOS
.MODEL _PMOS PMOS KP=10 LAMBDA=1M VTO=-4.1
R5 VDD 9 30
D4 VDD 9 _D2_MOD1
D5 9 VDD _D3_MODX
R3 7 3 1K
C2 3 VOUTA 7P
M3 9 10 VOUTB VOUTB _MTOP
R6 11 GND 1
C1 VOUTA GND 100P
EB1 7 VOUTA VALUE = {IF(V(VA) < 1.5 , -5 , 5)}
C3 3 2 0.5P
C4 3 4 0.5P
R4 VINA GND 100MEG
D6 GND 11 _DZ
M4 11 10 VOUTB VOUTB _PMOS
R7 12 10 1K
C6 10 VOUTB 7P
C7 VOUTB GND 100P
EB2 12 VOUTB VALUE = {IF(V(VB) < 1.5 , -5 , 5)}
C8 10 9 0.5P 
C9 10 11 0.5P
R8 VINB GND 100MEG
S3 17 18 VINA GND _S3_MOD
.MODEL _S3_MOD VSWITCH VON=2 VOFF=1 ROFF=10MEG
V7 17 0 DC=10
R9 18 GND 1
EB5 19 GND VALUE = {IF(V(18,GND) > 2.5 , 5 , 0)}
R10 19 VA 250
C11 VA GND 120P
S1 8 15 VINB GND _S3_MOD
V5 8 0 DC=10
R11 15 GND 1
EB3 21 GND VALUE = {IF(V(15,GND) > 2.5 , 5 , 0)}
R12 21 VB 250
C12 VB GND 120P
.ENDS UCCX7324
*$
.SUBCKT OR A B OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 | V(B)>0.5,1,0) }
.ends OR
*$
.SUBCKT RSFF_RDOM_VAR R S Q PARAMs:  T=10
EABM1  1 0 VALUE { If( V(S)>0.5 | V(Q)>0.5, 1,0)    }
EABM2  Q  0 VALUE { If( V(2)>0.5 & V(R)<0.5, 1,0)    }
R1   1 2 1
C1   2  0 {T*1e-9}
.ENDS RSFF_RDOM_VAR
*$
.SUBCKT TRFF_RDOM T R QP
EOUT2 S1 0 VALUE { IF( V(T1)>0.5 & V(Q)<0.5,1,0) }
C2         T2 0  10n  
R2         T3 T2  1  
EOUT3 R2 0 VALUE { IF( V(T1)>0.5 & V(Q)>0.5,1,0) }
EOUT6 T3 0 VALUE { IF( V(T)>0.5,1,0) }
EABM1  1 0 VALUE { If( V(S1)>0.5 | V(QP)>0.5, 1,0)    }
EABM2  QP  0 VALUE { If( V(1)>0.5 & V(R1)<0.5, 1,0)    }
R1   QP Q 1
C1   Q  0 20n
EOUT4 R1 0 VALUE { IF( V(R2)>0.5 | V(R)>0.5,1,0) }
EOUT5 T1 0 VALUE { IF( V(T3)>0.5 & V(T2)<0.5,1,0) }
.ends TRFF_RDOM
*$
.SUBCKT ANALOG_BUFFER IN OUT  
+ PARAMs:  GAIN=1
EOUT OUT 0 VALUE { GAIN * V(IN)}
.ends ANALOG_BUFFER
*$
.SUBCKT ANALOG_MUX A B SEL OUT  
EOUT OUT 0 VALUE { IF( V(SEL)>0.5,V(B),V(A)) }
.ends ANALOG_MUX
*$
.SUBCKT ANALOG_SUMMER IN1 IN2 OUT  
EOUT OUT 0 VALUE { V(IN1)+V(IN2)}
.ends ANALOG_SUMMER
*$
.SUBCKT CESR IN OUT
+ PARAMs:  C=100u ESR=0.01 X=2 IC=0
C	IN 1  {C*X} IC={IC}
RESR	1 OUT {ESR/X}
.ENDS CESR
*$
.SUBCKT COMPARATOR INP INM OUT  
EOUT OUT 0 VALUE { IF( V(INP)>V(INM),1,0) }
.ends COMPARATOR
*$
.SUBCKT COMPARATOR2 INP OUT  
+ PARAMs:  TH=1
EOUT OUT 0 VALUE { IF( V(INP)>TH,1,0) }
.ends COMPARATOR2
*$
.subckt DC_1mV_1A_1V_1nA A C
G1 A C TABLE { V(A, C) } ( (-1,-1n)(0,0)(1m,1) (2m,10) (3m,1000) )
.ends DC_1mV_1A_1V_1nA 
*$
.subckt GEN_DIODE 1 2 
D1 1 2 DI2D
.model DI2D D Is=1e-14 Cjo=.1pF Rs=.1
.ends GEN_DIODE
*$
.SUBCKT ILIMIT IN OUT PARAMs:  IP=1 IM=1 VHARD=10
EATAN      2 0 VALUE {ATAN(V(1))}
GABM1      IN OUT VALUE { if(V(2)>0,IP*V(2)/1.5708,IM*V(2)/1.5708)    }
E1         1 0 IN OUT {VHARD}
.ends ILIMIT
*$
.SUBCKT LDCR IN OUT
+ PARAMs:  L=1u DCR=0.01 IC=0
L	IN 1  {L} IC={IC}
RDCR	1 OUT {DCR}
.ENDS LDCR
*$
.SUBCKT LOAD P M
+ PARAMs:  TDELAY=1u TRISE=1u TFALL=1u TPULSE=1u TWIDTH=1 ISTART=1 IPULSE=2 RLOAD=1Meg
ILOAD P M PULSE({ISTART} {IPULSE} {TDELAY} {TRISE} {TFALL} {TPULSE} {TWIDTH} )
RLOAD P M {RLOAD}
GLOAD M P TABLE { V(M, P) } ( (-1,-1n)(0,0)(1m,1) (2m,10) (3m,1000) )
.ENDS LOAD
*$
.SUBCKT OP_AMP P M OUT 
+ PARAMs:  Hlimit=5 Rin=10Meg BW=18Meg DC_Gain=100 Rout=100 Llimit=0 SRP=1 SRM=1
R_Rin         P M  {Rin}
E_E1          5 0 M P {-Gain}
E_LIMIT2      6 0 VALUE {LIMIT(V(5), {-Abs(SRM)*Ca*1Meg+V(1)/Ra},
+                 {SRP*Ca*1Meg+V(1)/Ra})}
G_G2          1 0 6 0 -1
R_Ra          0 1  {Ra} 
C_Ca          0 1  {Ca}   
E_LIMIT1      2 0 VALUE {LIMIT(V(1),{Llimit},{Hlimit})}
V_VL          3 0 {Llimit+200m}
V_VH          4 0 {Hlimit-200m}
D_D1          3 1 Dideal 
D_D2          1 4 Dideal 
R_Rout        OUT 2  {Rout}
.model Dideal D Is=1e-10 Cjo=.01pF Rs=1m  N=1
.PARAM  Ra=1k   Ca={exp(DC_gain*log(10)/20)/(2*3.14159*BW*Ra)} 
+ Gain={exp(DC_gain*log(10)/20)/Ra} 
.ENDS OP_AMP
*$
.SUBCKT XOR A B OUT  
EOUT OUT 0 VALUE { IF( (V(A)>0.5 & V(B)<0.5) | (V(A)<0.5 & V(B)>0.5),1,0) }
.ends XOR
*$
.SUBCKT AND3 A B C OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 & V(B)>0.5 & V(C)>0.5,1,0) }
.ends AND3
*$
.SUBCKT AND4 A B C D OUT  
EOUT OUT 0 VALUE { IF( V(A)>0.5 & V(B)>0.5 & V(C)>0.5 & V(D)>0.5,1,0) }
.ends AND4
*$
.SUBCKT DELAY IN OUT
+ PARAMs:  T=100
S_S1         MEAS 0 RESET2 0 S1
E_ABM1         CH 0 VALUE { if( V(IN)>0.5,1,0)    }
E_ABM3         OUT 0 VALUE { if( V(MEAS)>0.5 & V(CH)>0.5,1,0)    }
R_R1         MEAS CH  {T} 
C_C1         0 MEAS  1.4427n  
E_ABM2         RESET 0 VALUE { if(V(CH)<0.5,1,0)    }
R_R2         RESET2 RESET  0.1  
C_C2         0 RESET2  1.4427n  
.MODEL         S1 VSWITCH Roff=1e9 Ron=1.0 Voff=0.25V Von=0.75V
.ENDS DELAY
*$
.SUBCKT FDP032N08  10 20 30
M1   1  2  3  3  DMOS L=1U W=1U
LD  10  1  1.5n
RD  10  1  1.8m
RS  40  3  0.5m
LG  20  2  6n
RG  20  2  59.54
CGS  2  3  6.8n
EGD 12  0  2  1  1
VFB 14  0  0
FFB  2  1  VFB  1
CGD 13 14  3.64n
R1  13  0  1.00
D1  12 13  DLIM
DDG 15 14  DCGD
R2  12 15  1.00
D2  15  0  DLIM
DSD  3 10  DSUB
LS   30 40  2n
RLS  30 40  20
.MODEL DMOS NMOS(LEVEL=3 VMAX=156k THETA=10.0m
+ ETA=2.00m VTO=3.90 KP=525
.MODEL DCGD D (CJO=3.64n VJ=0.600 M=0.680
.MODEL DSUB D (IS=975n N=1.50 RS=1.65m BV=75.0
+ CJO=3.09n VJ=0.800 M=0.420 TT=33.0n
.MODEL DLIM D (IS=100U)
.ENDS
*$
.MODEL MURS360T3 D  (IS=266.67E-12 N=1.4165 RS=34.006E-3 IKF=67.563E-3 ISR=2.1110E-3 NR=2.2286
+ BV=600 IBV=10.0u
+ CJO=78.0p  M= 0.727 VJ=1.8 N=2.27 TT=72.0n )
*$
.MODEL SSR8045 D BV=100 CJO=2.86N IBV=5M IS=26M N=2
+ RS=3.57M TT=14.4P
*$
.SUBCKT HUF75345S3S  DRAIN GATE SOURCE
M1 Drain 1 Source Source _MOS 
.MODEL _MOS NMOS KP=120 LAMBDA=2m RD=3m RS=3m VTO=3.5
Rb 1 Gate 5
CGS 1 Source 0.0295n
D1 Source Drain _DBOD 
.MODEL _DBOD D BV=66 CJO=5.621n IBV=250u IS=1.369E-5
+ M=0.503 N=2.142 RS=2.727m TT=32n VJ=0.667
C2 2 1 0.0487n
D2 2 Drain _DCRSS 
.MODEL _DCRSS D CJO=4.808n M=1.229 VJ=4.282
C3 2 Drain 62.69p
.ENDS
*$
.MODEL MMBT2907A PNP BF=360 BR=4.00 CJC=23.1p CJE=50.4p
+ EG=1.12 IKF=0.139 IKR=0.307 IS=8.79e-020 ISE=12.6f
+ MJC=0.300 MJE=0.500 NE=2.00 NF=1.00 NR=1.00 RB=4.84
+ RC=0.484 RE=1.21 TF=697p TR=84.5n VAF=139 VAR=20.0
+ VJC=0.300 VJE=1.10 XTB=1.5
*$
.MODEL UPR10 D
+ IS=820.68E-9 N=1.9505 RS=12.134E-3 IKF=.14249 CJO=100.00E-12
+ M=.3333 VJ=.75 ISR=100.00E-12 BV=100 IBV=100.00E-6 TT=5.0000E-9
*$
.SUBCKT BAT54_UCC2897A 1 3
R1 1 3 3.6E+07 
D1 1 3 BAT54S
.MODEL BAT54S D
+ IS=24.291E-9
+ N=1.0267
+ RS=1.0700
+ IKF=3.5113
+ CJO=15.008E-12
+ M=.53855
+ VJ=.61864
+ ISR=131.86E-9
+ NR=3.3642
+ BV=30
+ IBV=10.000E-6
+ TT=3.6135E-9
.ENDS
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 2
CINT Y 0 1.4p
.ENDS AND3_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 2
CINT Y 0 1.4p
.ENDS AND4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 100p
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5	
E_ABM Yint 0 VALUE {IF (V(INP) > 
+ V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT COMPARATOR2_1 INP OUT  
+ PARAMs:  TH=1
EOUT OUT 0 VALUE { IF( V(INP)>TH,0,1) }
.ends COMPARATOR2_1
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 100p
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT COMP_HYS INP INM HYS OUT PARAMs: T=10
EIN INP1 INM1 INP INM 1 
EHYS INP1 INP2 VALUE { IF( V(1)>0.5,-V(HYS)/2,V(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1),1,0) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 1K
.ends COMP_HYS
*$
.SUBCKT COMP_HYS2_new INP OUT 
+ PARAMs:  TH=1 HYS=0.1 T=10
EIN INP1 0 INP 0 1 
EHYS INP1 INP2 VALUE { IF( V(1)>0.5,-(HYS)/2,HYS/2) }
EOUT OUT 0 VALUE { IF( V(INP2)>TH,0,1) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 1K
.ends COMP_HYS2_new
*$
.SUBCKT COMP_HYS2 INP OUT 
+ PARAMs:  TH=1 HYS=0.1 T=10
EIN INP1 0 INP 0 1 
EHYS INP1 INP2 VALUE { IF( V(1)>0.5,-(HYS)/2,HYS/2) }
EOUT OUT 0 VALUE { IF( V(INP2)>TH,1,0) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 1K
.ends COMP_HYS2
*$
.SUBCKT COMP_HYS2_1 INP OUT 
+ PARAMs:  TH=1 HYS=0.1 T=10
EIN INP1 0 INP 0 1 
EHYS INP1 INP2 VALUE { IF( V(1)>0.5,(HYS)/2,-(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP2)<TH,1,0) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 1K
.ends COMP_HYS2_1
*$
.subckt srlatchrhp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5 
gq 0 qint value = {if(v(r) > {vthresh},-5,if(v(s) > {vthresh},5,0))}
cqint qint 0 1n
rqint qint 0 1000meg
d_d10 qint my5 d_d1
v1 my5 0 {vdd}
d_d11 myvss qint d_d1
v2 myvss 0 {vss} 
eq qqq 0 qint 0 1
x3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}
rqq qqqd1 q 2
eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}
rqb qbr qb 20 
cdummy1 q 0 1.44p 
cdummy2 qb 0 1.44p
.ic v(qint) {vss}
.model d_d1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.005
+ n=0.1
.ends srlatchrhp_basic_gen
*$
.subckt srlatchshp_basic_gen s r q qb params: vdd=1 vss=0 vthresh=0.5 
gq 0 qint value = {if(v(s) > {vthresh},5,if(v(r) > {vthresh},-5,0))}
cqint qint 0 1n
rqint qint 0 1000meg
d_d10 qint my5 d_d1
v1 my5 0 {vdd}
d_d11 myvss qint d_d1
v2 myvss 0 {vss} 
eq qqq 0 qint 0 1
x3 qqq qqqd1 buf_basic_gen params: vdd={vdd} vss={vss} vthresh={vthresh}
rqq qqqd1 q 2
eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})}
rqb qbr qb 20 
cdummy1 q 0 1.44p 
cdummy2 qb 0 1.44p
.ic v(qint) {vss}
.model d_d1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.005
+ n=0.1
.ends srlatchshp_basic_gen
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
X1 CLK CLKdel1 INV_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
R_CLK CLKdel1 CLKdel 21.64502165
C_CLK CLKdel 0 1n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}  
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, 
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS} 
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 1n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1 
Cdummy1 Q 0 1nF 
Cdummy2 QB 0 1nF 
.IC V(Qint) {VSS}
.MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 )
.ENDS DFFSR_RHPBASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT YINT Y 2
CINT Y 0 1.4p
.ENDS INV_BASIC_GEN
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 2
CINT Y 0 1.4p
.ENDS AND2_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 2
CINT Y 0 1.4p
.ENDS OR2_BASIC_GEN
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^  
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.443}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT2 YINT3 Y 2
CINT2 Y 0 1p
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
.subckt d_d1 1 2
d1 1 2 dd1
.model dd1 d
+ is=1e-015
+ tt=1e-011
+ rs=0.01
+ n=0.1
.ends d_d1
*$
.SUBCKT ASYMMETRIC_DELAY INP  OUT PARAMS: Rising_edge_Delay=1 VTHRESH=0.5 Falling_Edge_Delay=1 VDD=1 VSS=0
E_ABM1         YIN4 0 VALUE { if(V(YIN3) > {VTHRESH}, {VDD} , {VSS})    }
E_ABM2         YIN2 0 VALUE { if(V(YIN1) > {VTHRESH}, {VDD} , {VSS})    }
R_RINT         INP YIN1  1 TC=0,0 
C_CINT         YIN1 0  {1.443*Rising_edge_Delay}  TC=0,0
D_D10         YIN1 INP D_D1
R_R1         YIN4 OUT  1 TC=0,0 
R_ROUT         YIN2 YIN3  1 TC=0,0 
C_COUT         YIN3 0 {1.443*Falling_Edge_Delay}  TC=0,0 
C_C1         0 OUT  1n  TC=0,0 
D_D11        YIN2 YIN3 D_D1
.model D_D1 D
+ is=1e-015
+ tt=1e-011
+ rs=0.005
+ n=0.1
.ENDS ASYMMETRIC_DELAY
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},  
+ V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n 
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , 
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , 
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &  
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*$
.SUBCKT mmsz5242bt1 2 1
D1 2 1 MD1
.MODEL MD1 D IS=1.31137e-16 N=0.88099 XTI=1 RS=1.073
+ CJO=3e-11 TT=1e-08
R 1 2  MDR 1.1375e+10
.MODEL MDR RES TC1=0 TC2=0
RZ 2 3 0.295363
IZG 4 3 0.12
R4 4 3 190
D3 3 4 MD3
.MODEL MD3 D IS=2.5e-12 N=1.4997 XTI=0 EG=0.1
D2 5 4 MD2
.MODEL MD2 D IS=2.5e-12 N=2.41368 XTI=0 EG=0.1
EV1 1 5 6 0 1
IBV 0 6 0.001
RBV 6 0 MDRBV 11518.1
.MODEL MDRBV RES TC1=0.000651148
.ENDS mmsz5242bt1
*$
.MODEL DN4148 D(RS=.8 CJO=4PF IS=7E-09 N=2 VJ=.6V    
+ TT=6E-09 M=.45 BV=100V)
*$
.MODEL ES3B D (IS=7.27p RS=22.4m BV=100 IBV=10.0u
+ CJO=83.2p M=0.333 N=0.700 TT=36.0n )
*$
.SUBCKT XFOR_1P2S P1A P1B S1A S1B S2A S2B PARAMS: NP1=10 NS1=1 NS2=1 RP1=0.001 
+ RS1=0.001 RS2=0.001 LLEAK=100E-9 LM=0.01 RCORE=100e3 
R_R3         P1B 2  {RCORE}  
L_L1         P1A 1  {LLEAK}  
R_R1         1 2  {RP1}  
L_L2         P1B 2  {LM} IC=0 
E_E1         3 S1B 2 P1B {NS1/NP1}
R_R2         3 4  {RS1}  
F_F1         2 P1B VF_F1 {NS1/NP1}
VF_F1         4 S1A 0V
E_E2         6 S2B 2 P1B {NS2/NP1}
R_R4         6 7  {RS2}  
F_F2         2 P1B VF_F2 {NS2/NP1}
VF_F2         7 S2A 0V
.ends XFOR_1P2S
*$
.SUBCKT XFOR_CS P1A P1B S1A S1B PARAMS: N=100 
F_F1         S1A S1B VF_F1 {1/N}
VF_F1        P1B P1A 0V
.ends XFOR_CS
*$
.SUBCKT SPP20N60CFD_L0  drain  gate  source
Lg     gate  g1    7n
Ld     drain d1    3n
Ls     source s1   7n
Rs      s1    s2   1m
Rg     g1    g2     0.54
M1      d2    g2    s2    s2    DMOS    L=1u   W=1u
.MODEL DMOS NMOS ( KP= 15.089  VTO=4.95  THETA=0  VMAX=1.5e5  ETA=0  LEVEL=3)
Rd     d2    d1a  RdMOD  0.178 
.model RdMOD RES TC1=10m
.MODEL MVDR NMOS (KP=71.37 VTO=-1   LAMBDA=0.1)
Mr d1 d2a d1a d1a MVDR W=1u L=1u
Rx d2a d1a 1m
Cds1 s2 d2 67.3p
Dbd     s2    d2    Dbt
.MODEL     Dbt    D(BV=600   M=0.38  CJO=0.67n  VJ=0.5V)
Dbody   s2   21    DBODY
.MODEL DBODY  D(IS=3099280p  N=2.1  RS=7u  EG=1.12  TT=130n)
Rdiode  d1  21  RdiodeMOD  4.9m
.model RdiodeMOD RES TC1=4m
.MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)
Maux      g2   c    a    a   sw
Maux2     b    d    g2    g2   sw
Eaux      c    a    d2    g2   1
Eaux2     d    g2   d2    g2   -1
Cox       b    d2   5.3n
.MODEL     DGD    D(M=1.2   CJO=5.3n   VJ=0.5)
Rpar      b    d2   1Meg
Dgd       a    d2   DGD
Rpar2     d2   a    10Meg
Cgs     g2    s2    2.65n
.ENDS  SPP20N60CFD_L0
*$
.SUBCKT XFOR_GATE_1P2S P1A P1B S1A S1B S2A S2B PARAMS: NP1=10 NS1=1 NS2=1 RP1=0.001 
+ RS1=0.001 RS2=0.001 LLEAK=100E-9 LM=0.01 RCORE=100e3 
R_R3         P1B 2  {RCORE}  
L_L1         P1A 1  {LLEAK}  
R_R1         1 2  {RP1}  
L_L2         P1B 2  {LM} IC=0 
E_E1         3 S1B 2 P1B {NS1/NP1}
R_R2         3 4  {RS1}  
F_F1         2 P1B VF_F1 {NS1/NP1}
VF_F1         4 S1A 0V
E_E2         6 S2B 2 P1B {NS2/NP1}
R_R4         6 7  {RS2}  
F_F2         2 P1B VF_F2 {NS2/NP1}
VF_F2         7 S2A 0V
.ends XFOR_GATE_1P2S
*$