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Original question:

TPS3824: WDI pulse and can not RESET

TPS3824: Operation of RESET pin when VCC is stable of TPS3824

Akshay Shah
Prodigy 10 points
Part Number: TPS3824

Hi,

I have some confusion regarding the operation when VCC is stable. I have tried to explain my understanding through attached media. 

So as per my understanding if I want to tie my RESET(bar) pin to Logic '1' , I have to continuously apply WDI input of 100 ns (pulse) at every T interval while T < Tt(out)[Watchdog TimeOut] .

Let me know if I am missing anything in this.

  • 0
    TI__Genius 12630 points

    Hi Akshay,

    The way the TPS3824 works is that you have to supply a rising or falling signal at least 100ns wide (could be much wider) before the watchdog timeout of 1.6 seconds typical (0.9 second minimum) otherwise a /RESET transition to logic low will occur for the reset delay time of 200ms. Is this the behavior you are seeing?