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TLC6C5724-Q1: Why is M*data written twice on Figure 32 when M pcs of TLC6C5724-Q1 are connecting in cascade?

Part Number: TLC6C5724-Q1

 Hello guys,

 One of my customers is considering using TLC6C5724-Q1 for next their products.

 They have a question as the follow. Could you please give me your reply?

 Q. According to Figure 32 in the devcie datasheet, M*data written twice on Figure 32 when M pcs of TLC6C5724-Q1 are connecting in cascade?  

        Why is the data sent twice?

        I think it is enough to send M * data once. Is it miss-drawing?

 Your reply would be much appreciated.

 Best regards,

 Kazuya. 

  • becasue the 6c5724 are use shift resistor, and there are 2 device connect in cascade, if you want to write 2 FC-BC-DC Data into relavent device, you have to individul write and there are 2 M*data

  •  Hello Frank,

     Thank you very much for your reply.

     Do you mean that 2 device connect in cascade is Figure 31 schematic?

     If your answer is yes, I think "M*288 bits" of SDI on Figure 32 should be "288 bits" only without "M*".

    Also the latch rising edge between "Write FC-BC-DC Data" and "Write FC-BC-DC Data" should be not needed.

    Of course, the latch rising edge between "Write GS Data" and "Write GS Data" should be not needed.

     Is my understanding correct?

     Thank you again and best regards,

     Kazuya.

  • You comprehension is right ,the date only need to write once. For Figure32, the period 1 is a temple of writing FC-BC-DC data when the next flame is also FC-BC-DC data;

    The period 2 is a temple of writing FC-BC-DC data when the next flame is GS data; the difference between 2 period is the latch voltage level.TLC6c5724-q1 need the LATCH remain high during write FC-BC-DC data and remain low during write GS data. So the latch need to be pulled down-up-down.

  •  Hello Frank,

     Thank you very much for your reply.

     It is very helpful for the customer and me.

     Thank you again and best regards,

     Kazuya.