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TPS3808: open-drain RESET doesn't like to drive a simple logic buffer input

Erik Anderson41
Intellectual 925 points
Part Number: TPS3808

Hi,

Attaching the schematic, please find the upper right corner of the power circuit.  You can see that I've wire OR'ed two TPS3808's together.  The problem I observe is that the shared RESET signal is mostly low with a 110us high pulse every 20ms.  So, its basically stuck in reset.  why?  Well after a full day of troubleshooting, I find that if I simply disconnect the logic buffer input (A) of the SN74LVC1G34DBVR from the shared RESET signal, the shared RESET signal looks and acts as expected - that is it stays low during power-up and then goes high when the supplies are valid.  Just like a uP should act....

Why the heck would this logic buffer input do anything?  I am perplexed.  I've since changed the 4.7k pull-up to 20k pull-up per recommendation of the datasheet to be >10kohm.  I've also found (through experimentation) that its only the 5V TPS3808 IC that has a problem with the buffer.  The 3.3V TPS3808 is fine.

Why does the TPS3808 care about what's connected to its RESET line at all?  Shouldn't it only care about VDD / SENSE / MR?  The functional diagram just shows a simple MOSFET open-drain.  Is there a fighting of supplies somewhere and an ESD diode is getting forward biased?  I just don't see it, please help!7652.power.pdf

thanks,

Erik

  • 0
    TI__Genius 9375 points

    Hi Erik,

    This is a perplexing issue. My initial guess that it has something to do with the internal ESD diodes of the device. That being said, the TPS3808 does care about the RESET line because of the open-drain output. Anything including the resistors that can affect the logic levels of the device could cause high leakage into the IC.

    Thanks,
    Abhinav.

  • 0 in reply to Abhinav.Sharma
    Intellectual 925 points

    Just wanted to come back and share what the issue was.  The two LT switchers were pulling lots of in-rush current and tripping the 5V supply.  It would oscillate at the timeout period if the RESET signal because of the repeated on/off enabling of the LT switchers.  So of course when I disconnected the logic buffer (which was enabling the LT switchers) the circuit behaved itself.  This was one of those problems where I was chasing the wrong thing until I could see that there was a dip in the 5V supply.

    Anyways, thanks for the help and reply!

    Erik