• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 2 answers
  • Subscribers 64 subscribers
  • Views 816 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS65023: Request help to review schematic design using TPS65023RSBTG4

Chang Fei Yee
Prodigy 130 points
Part Number: TPS65023
Other Parts Discussed in Thread: LM3881,

Hi TI,

I am currently designing a power supply with power up sequence using TPS65023RSBTG4. The schematic is shown below.

Could you please review if the design is correct? Thanks.

  • 0
    TI__Expert 4690 points

    Hi,

    This thread has been assigned to the applications engineer supporting this devices. 

    Could you please upload the design again. It seems like there was an issue uploading the file.

    Regards,
    Ivan 

  • 0 in reply to Ivan Calzada
    Prodigy 130 points

    Hi,

    Please review the schematic shown below (pasted in this text box). thanks.

    If image is not visible, is there a link to upload the image file?

  • 0 in reply to Chang Fei Yee
    TI__Mastermind 30310 points

    The image is not visible.

    In the text editor, you need to click the paperclip symbol (says "Insert File" if you hover over) to attach a PDF or other file type or the Image+ symbol (says "Insert/Edit Media" if you hover over) to insert an image (.PNG, .JPEG, .GIF) in the body of your message.

    Both symbols are highlighted in the below image, which was inserted using the Image+ symbol to "Insert/Edit Media" and added a .PNG screen shot saved on my PC.

  • 0 in reply to Brian Berner
    Prodigy 130 points

    Hi, I inserted the image file. Could you please review? Thanks.

  • 0 in reply to Chang Fei Yee
    TI__Mastermind 30310 points

    Yes, I will review and provide my feedback now that I can see the image :-)

  • 0 in reply to Chang Fei Yee
    TI__Mastermind 30310 points

    Below is my feedback, based on TPS65023x Schematic Checklist document:

    • Even if VRTC is un-used, recommendation is "to connect at least 100nF cap" from the VRTC pin to GND
    • If PWRFAILz output is un-used (floating), then PWRFAIL_SNS input should be connected to GND
    • If LOW_BATz output is un-used (floating), then LOWBAT_SNS input should be connected to GND
    • Cannot see pull-up resistors connected to SCLK (FPGA_SCL) and SDAT (FPGA_SDA) pins - should be 1k to 10kOhms
    • Cannot see FLAG1-3 source of signals that controls EN_DCDC1-3 inputs to ensure your desired timing of Seq. 1 = DCDC2, Seq. 2 = DCDC3, Seq. 3 = DCDC1
    • Because both LDOs are un-used, you can connect both LDO1 & LDO2 pins directly to GND (same as VIN_LDO)

    You can refer to the attached Checklist file that I started for you.

    TPS65023_CHKLST_2020-08-03.xlsx

  • 0 in reply to Brian Berner
    Prodigy 130 points

    Thanks Brian.

    Could you please review the pwr seq schematic using LM3881 shown below?

  • 0 in reply to Chang Fei Yee
    TI__Mastermind 30310 points
    • DCDC1_EN = FLAG3 = Sequence #3
    • DCDC2_EN = FLAG1 = Sequence #1
    • DCDC3_EN = FLAG2 = Sequence #2

    Result: when EN pin of LM3881 is >1.22V (t0), the sequencer will start operation. Since INV = GND (Low), FLAGx outputs are active-high which is correct for controlling the TPS65023 PMIC.

    1. 1.0V (DCDC2) will be enabled by FLAG1 at time t0 + TD1
    2. 1.8V (DCDC3) will be enabled by FLAG2 at time t0 + TD1 + TD2
    3. 1.5V (DCDC1) will be enabled by FLAG3 at time t0 + TD1 + TD2 + TD3

    T_enable_delay = 1.22V * CEN / 7uA = 0 because there is no capacitor at the EN pin to create an RC delay during startup. When "+3.3V" net > 1.2V, sequencer will start.

    The image is hard to read, but it looks like the capacitor at TADJ pin, C390, has a value of 0.0047uF

    TADJ,period = 120us/nF*0.0047uF = 0.564ms

    TD1 = 9*0.564ms = 5.076ms Min, 10*0.564ms = 5.64ms Max

    TD2,TD3 = 8*0.564ms = 4.512ms typical

    These are the sequence order and timing parameters for the LM3881 as it has been implemented in your system.

    Since I do not know the FPGA that is being powered the TPS65023 device, you will need to determine if the sequence timing and order will meet the sequencing requirements of the FPGA.

  • 0 in reply to Brian Berner
    Prodigy 130 points

    Hi Brian, thanks very much for the review.