Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 64 subscribers
  • Views 280 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

UCC29002: Common mode range of current amplifier in low side sensing applications

UCC29002: Common mode range of current amplifier in low side sensing applications

Andrew Fendrich
Prodigy 70 points
Part Number: UCC29002

Does biasing the CS+ and CS- pins below ground degrade the effectiveness of the current amplifier as long as it does not exceed -0.3V common mode?

In a previous posting I asked whether the CS+ and CS- pins can be placed below the gnd pin of the IC.  The datasheet calls out -0.3V as an absolute potential at these pins.  With the sense resistor placed in the ground path, I have seen suggestions that the ground line be biased to the load regulation point.  This not only forces the CS+ and CS- pins below ground by the drop across the current sense resistor, but also any cabling drops will also bias this point below ground.  My question is whether the current sense amplifier is capable of representing the current successfully with these pins operating below ground of the IC.

  • 0
    TI__Mastermind 32500 points

    Hello Andrew,

    Thank you for your interest in the UCC29002 current-sharing controller.

    Operating the current sense below ground within the -0.3V common-mode limit does NOT degrade the effectiveness of the current sense amplifier.
    In other words, it is okay to do this.  Actually a similar situation exists in a high-side sense application where the UCC29002 is powered from the output rail that it is sensing. Then the abs-max limit is VDD + 0.3V. 

    The +/- 0.3V number comes from internal p/n junction voltages between the pin node and the substrate silicon which is basically GND.  The idea is to prevent negative (or positive above VDD) excursions more than a diode-drop below GND to avoid injecting charge into the substrate. This charge is uncontrolled where it can go, and it could disrupt operation of any nearby circuit unpredictably.  0.3V is used because the p/n drop reduces with junction temperature (like any diode) and the device must operate up to 105C. 

    Rcable must be low enough to avoid impressing more than -0.3V on either of the CS inputs.

    Regards,
    Ulrich