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Original question:

TPS650864: Kindly Review the Schematic of TPS6508641 for timing attached for MPSOC Schematic Design

TPS650864: ReOpen: Schematic Review of existing thread

Shyam Daram
Expert 1275 points
Part Number: TPS650864
Other Parts Discussed in Thread: CSD87381P

Hi, 

Kindly go through the related thread, of review of MPSOC power design based on TPS6508641

I have realized my Circuitry using the attached SCH which is reviewed previously in related thread.

But now after realization of design, the MPSOC 6CG device is stuck in PMIC sequence

Also, find the PMIC sequence followed in same attachement.

All Bucks shown in the sequence are used and nothing is left un-loaded

SCH & Sequence Diagram: /cfs-file/__key/communityserver-discussions-components-files/196/4062.Aug1_5F00_PMIC_5F00_0p72_5F00_review.pdf

The problem arises at :

1. the sequence completes some times and not sometimes, this is a strange behaviour, is it due to problem with any of rail ?, i checked all rails and there are no shorts discovered

2. Rail voltages in the sequence are as follows

VSYS : 12V , its 12V no issue(not part of PMIC as you know)

LDO5 and LDO3P3 : up and read 5v and 3.3v, no issue they have enabled the 0.72v regulator which further issued PGOOD which is connected to CTL4 of PMIC

BUCK1 : read 5V and proper

BUCK2 : 0.85V rail, but this reads 0.80 which is worrisome , but still sequence continued

BUCK5 : 1.2 rail, but this reads 1.16, anything to worry ?

BUCK6: Not up, i am stuck here, when board is powered BUCK6 output shows a short with GND, when not powered up this shows 240 ohm.

3. as said before this passes momentarily during which i could not measure the voltages, so in short the sequence completes and restarts again and sometimes keeps on flickering.

4. RLIM2 is 11k resistor is it what causing 0.85 to read 0.80 ?, am i not able to provide enough current required by load

if RLIM2 is 11k what would be maximum current ?

My calculation : (Rlim * Ilimref) / (Rdson * 8*1.3) + (Iripple/2) = Ilim 

so for RLIM being 11k it would correspond to (11k * 50uA) / (3 *8 * 1.3) + (ignore for approximation) = Ilim

this would bring Ilimit to 17mA which is unrealistic, i think i am mis calculating the values

Kindly help me what would be the max output current for Rlim 11k  ? 

5. Pin 1 FBGND2 is directly grounded rather than being connected to a negative terminal of output cap, will this create any issue ?

  • 0
    TI__Genius 12735 points

    Hello,

    Please see my answers for your questions below.

    1. It is possible you are having an issue with one of the rails starting, however it is difficult to speculate this without seeing scope shots of each of the rails during the power up sequence. Using an oscilloscope should allow you to see which rail is failing to startup properly and should simplify the debug.

    2. As you mentioned on number 5, you tied the FBGND2 pin to a ground generically near the PMIC. This will impact what the output regulation for Buck 2, specifically if you have tied it directly to the thermal pad. Can you post a screenshot of the layout for this pin? I would not expect to see Buck 5 at 1.16V but before knowing more about the Buck 2 layout I am hesitant to be concerned about Buck 5.

    3. I would recommend taking scope shots of every rail, starting with the beginning of the sequence on page 34 of the TPS650864x datasheet.

    4. The calculation needed for RILIM2 would be as follows:

     

    This calculation matches what you posted above, however the Rdson of the FET you are using is in mΩ and you calculated using Ω. By correcting this, the equation results in a current limit of 17.63A. However, after looking at the CSD87381P datasheet, I believe the Rdson should be 6.3 mΩ for your case. This would give you a current limit of 7.55A. Can you explain where you got the 3mΩ value?

    5. I addressed this in #2. 

  • 0 in reply to Layne J
    Expert 1275 points

    Please find the attachment with PMIC layout ,scope shots and sequence shots.

    /cfs-file/__key/communityserver-discussions-components-files/196/0602.PMIC_5F00_Review_5F00_PostDesign.docx

    i have found FBGND2 being tied to the bottom layer ground rather than the thermal pad which seems ok.

    i have shared the my complete board layout brd and schematic pdf  file to your mail id.

  • 0 in reply to Shyam Daram
    TI__Genius 12735 points

    Hi Shyam Daram,

    Thank you for providing that information. I will go through this information and provide some feedback tomorrow, Wednesday. 

    Best regards,

    Layne J

  • 0 in reply to Layne J
    TI__Genius 12735 points

    This thread is being taken to email and a final resolution will be posted on here when completed.

    Layne J