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UCC28780: ucc28780

robin gangopadhya18
Mastermind 6055 points
Part Number: UCC28780

Ulrich:

Hello!

mayday mayday...

Even after review of the troubleshooting document & modifying certain values as suggested by the document - including substantial reduction in  Lpri & adj of Np/NA ratio, we are still at 0 PWML.

Pl see attached results in ppt form.

I attached updated sch in pdf. There are a few things temporary in the sch: such as D1 & D8., Doubt if they impact startup but will change as soon as we get these parts.

It seems our Vdd discharges faster than Eval kit . And that is the root cause of the problem, maybe?

I have of course hunted down all possible reasons. Including PCB, DCR value across VDD caps which is about the same as the eval kit.

There is nothing across Vdd caps now in our circuit. All functions are relegated to "bias:" obtained from external 5.2V supplied which drives SN6505 as you can see in the sch.

So what would cause VDD to drain out through the controller as soon as Vdd hits 17.5 V in our circuit but not in the Eval kit? have exhausted all possibilities. But I am looking for the last one we could not fathom.

Any help will be immensely appreciated.

robin

proto2_vdd_hvg_startup_no_run.pptxprotoeq304ly_PRISEC_proto1notes.pdf

  • 0
    TI__Genius 9790 points

    Hi, Robin

    I've assigned your thread to Uli. please wait for his response.

  • 0 in reply to Yunsheng Qu
    TI__Mastermind 31670 points

    Hello Robin,

    On slide 5 of your pptx, it looks like REF can only get to ~3V (I assume the waveforms are X10 of the voltage/div scales).

    REF is not simply a reference output but actually powers most of the circuitry within the IC.  It must be "in-spec" for the IC to function, and that is basically Vref > 4.8V.   It appears that something is loading down the REF output to its current limit and prevent further power up. Since there is about 3V, it is not a dead-short.

    Please investigate the REF net and see if anything is abnormally loading it.  It is only "good" for about 5mA max external load and that level is not really recommended. Aside from the BUR network (which can be temporarily disconnected for test), it looks like REF goes to a connector pin off-board.
    Check that loading, too, please.

    On the pcb, the GNDEXT plane should NOT run under RDM and RTZ nets to avoid stray capacitance on these nodes, but that is not the problem here.
    maybe later it might or might not be.

    For now, if REF can't get to 5V, nothing will work.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Mastermind 6055 points

    Ulrich:

    Yes, this is the response I did not see until you met5njioned  about it...

    Yes, REF is definitely not right & needs a thorough check-up.

    It goes not go to many places- only to the feedback to fb node through a cap...checking

    Bear in mind, we will redo the PCB as soon as it makes sense to do so. That will be like closing the loop, making some measurements including stability just to record data...some temp data..continued funding depends upon that.

    In this proto run, I have 3 more pcbs left. Hope to run them through this cycle .