Hi,
We have a design requirement for reset timing.
The SYSRST_N work timing is (20-100ms) after the E1602 power ready (~need 6.5ms)
When E1602 power on ready then SYSRST_N is ready (20ms-100ms)
Would you check our reset design circuit of TPS3703B is correct, please? Thank you
TPS3703B_TOTICHECK_20200925.pdf
TPS3703B_TOTICHECK_20200925.pdf