Hi,
I intend to use ISO5852s as a high-side gate driver. The bias supplies (VCC1, VCC2, VEE2) comes from the output of three LDOs which generate +5V, +20V and -5V respectively. These voltage rails are generated from the secondary of an isolation transformer. However, all three voltage rails share the same ground as the reference point in the transformer winding for the three voltages is the same. The isolation for the PWM signal is provided by optical transceiver. Therefore, isolation barriers for both the PWM signal and the bias supplies are created in this way. However, when I turn on the power supply at the primary side of the transformer, I get +18V, +5V and -5V buses at the output of the LDOs which are fed to VCC2, VCC1 and VEE2 respectively. a 10 kHz PWM signal provided at the input is transferred over the optical fiber and between IN+ and IN- I measure a PWM signal with high (5V) and low (1V). However, when I measure the voltage across the G( OUTH) and S (OUTL) terminals, I notice the output voltage is clamped to -VEE2. The indicator pin statuses are as as follows.
1. FLT: High
2. RDY: High
3. RST: High
I have tied the DESAT pin to GND. In addition, as you can understand due to the configuration of the transformer secondary, GND1 and GND2 are actually same node. Any suggestion underscoring the reasoning of the problem of Vgs being clamped to the level of Vee2 is appreciated in advance.