This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO5852S: Vgs clamped to the level of VEE2

Part Number: ISO5852S

Hi,

I intend to use ISO5852s as a high-side gate driver. The bias supplies (VCC1, VCC2, VEE2) comes from the output of three LDOs which generate +5V, +20V and -5V respectively. These voltage rails are generated from the secondary of an isolation transformer. However, all three voltage rails share the same ground as the reference point in the transformer winding for the three voltages is the same. The isolation for the PWM signal is provided by optical transceiver. Therefore, isolation barriers for both the PWM signal and the bias supplies are created in this way. However, when I turn on the power supply at the primary side of the transformer, I get +18V, +5V and -5V buses at the output of the LDOs which are fed to VCC2, VCC1 and VEE2 respectively. a 10 kHz PWM signal provided at the input is transferred over the optical fiber and between IN+ and IN- I measure a PWM signal with high (5V) and low (1V). However, when I measure the voltage across the G( OUTH) and S (OUTL) terminals, I notice the output voltage is clamped to -VEE2. The indicator pin statuses are as as follows.

1. FLT: High

2. RDY: High

3. RST: High

I have tied the DESAT pin to GND. In addition, as you can understand due to the configuration of the transformer secondary, GND1 and GND2 are actually same node. Any suggestion underscoring the reasoning of the problem of Vgs being clamped to the level of Vee2 is appreciated in advance.

  • HI Wasekul, Thanks very much for your question.

    If you drive high side driver, then VCC1 cannot be using the same ground reference as VCC2 and VEE2. Can you please double check? since it doesn't sound correct from my side.  refer to your description. "However, all three voltage rails share the same ground as the reference"

    If you are driving high side, there will be common mode voltage between VCC1 and VCC2/VEE2. this common mode voltage can be as high as your high voltage bus voltage.

    I am confused why is opto coupler used to drive PWM since ISO5852s already has signal isolation.

    It would be best if you can draw a simplified diagram to better understand what you are describing and we will help you from there.

    Thanks.

    Wei

  • Hi,

    Thanks for the reply. The objective is to drive a HV MOSFET (10 kV) in high-side configuration. Therefore, I have used isolation transformer for the necessary voltage isolation for the power supplies of the gate driver and optical fiber link to isolate the PWM signal. I am attaching a simplified diagram herewith.

  • Hi,

    In addition, in a separate attempt, I have decoupled the logic side gnd (GND1) and power side gnd (GN2) to narrow down the problem. I have used 3 seperate power supplies for VCC1, VCC2 and VEE2. In this scenario, the ground of the PWM signal and VCC1 is same while the ground (GND2) of VCC2 ad VEE2 is same but different from the one from the logic side (GND1). However, I am not getting level shifted PWM output across the G-S terminal. I am getting a DC negative voltage. I am posting the modified connection diagram for your reference.

  • Hi Wasekul, Thanks very much for your information. 

    it seems the image was not attached successfully. It doesn't support copy/paste, you can edit by attach a attachment or image.

    1. One more thing I'd like to share. The in+ and in- are independent signal, can you please measure IN+ to GND1 and IN- to GND1 respectively. Only high logic on IN+ and Low in IN- will deliver the signal to output side. see truth table 1 on page 23.

    2. I would also recommend to desolder this unit and populate a new chip and try it again. Your setup looks OK to me and it should switch accordingly.

    Thanks.

    Wei