• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Answers 3 answers
  • Subscribers 63 subscribers
  • Views 536 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

[FAQ] BQ25710, BQ25713, BQ25713B, BQ25700A, BQ25703A, BQ25708 - Schematic Review Design Tips

BQ25703A: charge and discharge current path in BQ25703ARSNR

Akshata Bilagi
Prodigy 50 points
Part Number: BQ25703A

Hi Team,

I am using BQ25703ARSNR. I would like to understand the current charging and discharging path in this tool/reference design. "6712.BQ2571X_SchematicChecklist_CalculationTool"

Regards,

Akshata

  • 0
    TI__Mastermind 24075 points

    Hi Akshata,

       I would recommend using that resource as a supplemental tool when designing schematic. For a theoretical understanding please refer to the datasheet here: www.ti.com/.../bq25703a.pdf

  • 0 in reply to Kedar Manishankar
    Prodigy 50 points

    I already checked datasheet. I am using RRC2057 battery in my system. Max. charge current: 4480mA and Max continuous discharge current is 8000mA. And I am using design similar to "6712.BQ2571X_SchematicChecklist_CalculationTool". How's changing and discharging both is done here? Can you please explain a bit detail. Can you please support reviewing our schematics?

    I am attaching the same.. Charger_20201013.pdf

  • 0 in reply to Akshata Bilagi
    TI__Mastermind 24075 points

    Hi Akshata,

        Charging and discharging measurement are done by sensing current across the sense resistor between SRP and SRN. The information is covered in the datasheet under section 8.3.5.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)

  • 0 in reply to Kedar Manishankar
    Prodigy 50 points

    I have few more questions.

    1. In my design attached, Q2 allows to flow current from Vsys pin of charger to (+V_CHGR_SW_L) to battery(+VBATTERY) while charging. While discharge how does current flow?

    2. U1 and U2 MOSFET outputs are shorted. What is role of U1 MOSFET? and U2 MOSFET? How buck and boost work here?

    3. I am unable to understand the current flow here as well. Do you have any video or any other source where detailed explanation is given about IC and reference designs? 

    4. How to calculate the in and out currents from each of these?

  • 0 in reply to Akshata Bilagi
    TI__Mastermind 24075 points

    Hi Akshata,

    1.    In normal charging mode when adapter is present, charge current is sensed across the SRN, while output of the converter (SYS) is either regulated at VSYSMIN or tracks battery voltage (you can refer to datasheet for more operation on BATFET linear mode operation). In this way the charge current passes from SYS to BAT through BATFET so we can supply both charge current as well as SYS load from output of converter. When adapter is absent, and to still ensure SYS rail is not lost, the battery will supply SYS voltage directly so current will flow in opposite direction as discharge current from battery to supply SYS load.
    2. Where are the LSFET to be driven by LODRV1 and LODRV2 in your schematic? I see U1 and U2 which are driven respectively by HIDRV1 and HIDRV2. The FET driven by HIDRV1 is the high side FET for buck mode operation and the FET driven by HIDRV2 is the boost mode high side FET. 
      1. I think there is a misconception regarding the operation of converter here. Please refer to the EVM user guide as well as the checklist above to see the required components in your schematic
    3. Section 8.3.4 Converter Operation describes operation of the 4 switching FET in Buck, Boost and Buck Boost operation. Based off of standard buck and boost converter theory you will be able to visualize the current flow once you refer Table 2. MOSFET Operation under this section

  • 0 in reply to Kedar Manishankar
    Prodigy 50 points

    U1 and U2 are dual n channel MOSFETS. We have used them to save space. Please review if our design is proper.

  • 0 in reply to Akshata Bilagi
    TI__Mastermind 24075 points

    Hi Akshata,

       Yes you are right, I can see the LODRV net connected properly. The power stage design is accurate, correct COMP1 COMP2 configuration, correct IADPT setting etc. Schematic looks good to me.