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Original question:

[FAQ] TPS65086: How do I program sequencing?

TPS650864: CTLx power sequencing

Dennis McGlumphy
Expert 1390 points
Part Number: TPS650864
Other Parts Discussed in Thread: TPS650861

Dear Sirs

I am using the TPS6508641 PMIC to power a Xlinx UltraScale.  On page 52 of the TPS650864 data sheet sec. 6.10.1 it is written, "The device has six control-input pins (CTL1–CTL6) to control six SMPS regulators, three LDO regulators, and three load switches. This allows the user to define up to six distinctive groups, to which each VR can be assigned for highly flexible power sequencing.".  I can not find the default control-pin mapping.  Which control-pin controls which SMPS, LDOs and load switches?

  • 0
    TI__Genius 17380 points

    Hello,

    The NVM settings can be found in the "TPS6508641 Design and Settings" section. If you have rev C, it is section 6.5. If you have the newly released rev D (new format, no TPS6508641 information changed), it is section 8.5.

    The power up / power down sequences are the clearest way of seeing what impact the CTLx pins have and how the GPOx pins respond. They are also described in text format below the TPS6508641 Low Power States graphic. 

    The other way you can look at the settings is to go to the TPS650861 product folder, go into the "Design and Development" and under "Design tools & simulations" is TPS65086100 OTP Generator for Xilinx Zynq Ultrascale+ (TPS6508641 settings) (Rev. A) which contains the default NVM settings for the TPS6508641. The TPS650861 is the user programmable version of the TPS650864 family so if you wanted to slightly modify the settings, you could start with a TPS650861 instead.

  • 0 in reply to Kevin LaRosa
    Expert 1390 points

    Dear Mr. LaRosa

    I'm sorry I haven't gotten back to you sooner.  Our office was shut down due to COVID.  As to you reply, I reread the power-up sequencing (fig. 6-11).  This is my understanding.  Please correct me if I'm wrong.  CTL4 controls Buck1.  CTL3 controls Buck2,GPO1, Buck5, Buck6, LDOA2, VTT LDO, LDOA1Buck3 and Buck4.  CTL5 controls GPO4SWB1_2, LDOA3 and GPO3.  Are these control lines independent of each other?  In addition, I read the text following the low power states fig. 6-13 page 36.  In the second paragraph, it states that CTL3, CTL4 and CTL5 can be tied together.  Does this mean that all the sequencing will start together, that is Buck1, Buck2 and GPO4 all start at the same time? 

  • 0 in reply to Dennis McGlumphy
    TI__Genius 17380 points

    Hello,

    You are correct on which CTL pins control which regulators. They are not independent except CTL2, which states "CTL2 is used to enable and disable SWA1 and is independent of the rest of the sequence".

    For example, from the graph, the state of CTL3 is a do-not-care prior to BUCK1_PG being available. If all CTL pins are tied together, the sequence will look exactly like Figure 6-11. 

  • 0 in reply to Kevin LaRosa
    Expert 1390 points

    Dear Mr. LaRosa

    Thank you for your time.  I think I understand want is going on.