• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 63 subscribers
  • Views 689 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMZM33604: Theta JA vs PCB Area

Stefan Timm
Prodigy 40 points
Part Number: LMZM33604

Hi all,

I'm looking for additional data for the Theta JA vs PCB-Area from 5 to 15 cm². I'll use the LMZM33604, but not at full output poewr and max. ambient temperature of 50°C, looking for the minimum required PCB area to get Rth of ~40K/W.

Thanks for help.

Best regards

Stefan

  • 0
    TI__Guru 50120 points

    Hi Stefan,

    What is your operating conditions (VIN,VOUT,IOUT) and how large can you make your board to be?

    As you see in the datasheet, the graph is between 15cm^2 to 105cm^2. I used an online digitizer tool to get the datapoints on Figure 52 for a common 4 layer board between 15cm^2 to 35cm^2. Then I replotted in excel to get the linear equation to get the extrapolated data below 15cm^2. Since I don't think the graph can be linearly extrapolated below 15cm^2 I decided to also add a  "worse theoretical" as a rough estimate of what I think the graph might look like at lower board areas. 

    I made a rough and quick calculator tool to help visualize this.LMZM33604 PCB Area Approximation.xlsx

    Again Figure 32 is based off real bench data test. However this excel sheet extrapolates that data with rough estimates for lower board area and should be used only as a reference. Ultimately, you would need to test your board to see if it has enough copper area for board areas lower than 15cm^2.

    Regards,

    Jimmy 

  • 0 in reply to Jimmy Hua
    Prodigy 40 points

    Hello Jimmy,

    thanks for your effort. Actually I'm planning to put 2 modules LMZM33604 on one board, one is for 12V/2A  one is for 5V/3A max. So the maximum power loss should be 2W each. With a max. ambient temperature of 50°C, I need max. 37.5K/W for each device. Board size is as always a matter and should be not too big. That's why I'm thinking of 30x30mm² for each module. I was hoping to receive some answer from a TI employee, if there is data available for smaller board sizes.

    Of course I guess I need to do some test boards, but it's always nice to know as much as possible in advance.

    Best regards and thanks again for your fast answer ;-)

    Stefan

  • 0 in reply to Stefan Timm
    TI__Guru 50120 points

    Hi Stefan,

    Thank you for the update. 30mm x 30mm = 9cm^2 board area per module. I think this sounds reasonable given that you are not pulling that much output power. Ideally you'd want to equally space these two components apart to prevent coheating. 

    I'd make sure to use at least a 4 layer board with the following layer stackup for optimal thermal performance ( 2 oz copper top and bottom layer, 1 oz copper on inner layers).

    Hope this helps. 

    Regards,

    Jimmy 

  • 0 in reply to Jimmy Hua
    Prodigy 40 points

    Hello Jimmy,

    thanks again for your answers and sorry for my late reply.

    One additional question concerning the proposed layout in the datasheet came up here. In my opinion, inner layers don't contribute that much to the heat transfer away from the module, while most of the dissipated power will be radiated via top and bottom layer copper planes. So I'm curious why bottom layer is on AGND which is only connected with 3 vias to top layer copper and the module? Wouldn't it be better to have bottom layer on PGND?

    Best regards

    Stefan

  • 0 in reply to Stefan Timm
    TI__Guru 50120 points

    Hi Stefan,

    I see what you are saying and mostly agreed that it would have been better to have the bottom layer as PGND. The engineer creating the EVM could have made Mid layer 1 AGND for the analog component return path connections and bottom layer PGND for even better thermal performance.  

    I think the main factors for thermals is large PGND copper plane, proper thermal vias on PGND to connect inner layers, and isolated copper island for SW pins under device for thermal relief. If you follow these PCB recommendations, you should have a decent design.

    Regards,

    Jimmy 

  • 0 in reply to Jimmy Hua
    Prodigy 40 points

    HI Jimmy,

    thanks for clarification. That's what is mentioned in the document "Thermal Characteristics of Various DC/DC Module Packages", too.

    Best regards

    Stefan

  • 0 in reply to Stefan Timm
    TI__Guru 50120 points

    Thanks for using the E2E forum. I'll be closing this thread now.