LMG1205: LMG1205 HO "latch up" malfunction, stays "high" during ~300 ns for apparently no resaon during high current, high dv/dt situations

Hello Ernest,

Thanks for the detailed information.

I have reviewed the scope plots and schematic and I have several comments regarding the issues:

1. There appears to be false logic with the last waveform (as you pointed out) clearly showing the HO staying high while HI is low. This is likely due to the fact that after the first falling edge of the HI, the input stage seems to be already damaged with the oscillation on HI pin reaching negative transient down to ~-10V which well beyond the input capability.

2. I believe the shoot through on the bridge is likely triggered by high di/dt current coupling to the low-voltage stage resulting in input signal oscillations violating the abs max ratings of the logic stage of the driver consequently causing false logic where you're seeing the increased falling prop delay on HO as it is not promptly responding to low commands.

As possible workaround solutions, I appreciate that you have already tried several things already. I want to suggest few things to try to maintain signals on the driver within the recommended operating conditions:

a. I know you have already tried several value but I'd like to increase input capacitors to 100-200pF with the following recommendations.

b. To limit the dv/dt at the gate and slow down di/dt through the FETs, let us increase gate resistors (both adding a resistor on HOL and increasing HOH) while adding placeholder 10 to 100pF Cgs capacitors close to the gate.

c. Adding 10k resistors close to the gate to pull gate low when input signal if OFF in the event parasitic current is coupled to the gate through Cgd capacitor.

d. Clamp diodes on input pins to maintain the signal within the recommended operating conditions.

e. If the recommendations above do not improve, then I'd suggest a ferrite bead with similar impedance (at the switching frequency) as the input resistor to limit the oscillations.

If you're still do not see improvements at that point, please let us know for further review on the layout and more recommendations.

Regards,

-Mamadou 

Hi Mamadou,

thank you for the answer. I agree that the HI and LI signals are well outside the nominal values during transients.

So yes, we are going to test different values of input filter capacitors. Let's see with 200 pf (a) and clamp diodes on PWM inputs (d). And then the points that require layout change and we cannot currently modify. (b,c).

I will keep you updated.

Regards,

Ernest

Yeah I agree, let us try the updates that do not require any board modification first.

Kindly post on this thread when you have updates.

Regards,

-Mamadou

Hi Mamadou,

I have tried with NP0 200 pF and 330 pF between VSS and HI, and LI as physically close as possible to to the gate driver (<1 mm) and the problem persists. A slight variation of the self-oscillation is observed and the undershoot is smaller but still causes malfunction.

Added an ultrafast Schottky in parallel with those capacitors to clamp the negative peak does not resolve the issue either. 

So I think that the best way to proceed is to modify the PCB layout adding non-zero turnoff resistance and improving the layout whenever possible.

-Ernest

Hello Ernest,

Thanks for the updates.

I agree, let us include placeholder protective components around the driver (mentioned above) that you may DNP when not required.

During PCB revision, you may separate GND (power vs digital) to short them on a single point through a net tie. 

You may also bring the power stage closer to the driver for tighter layout (if it is not currently the case) and small GND return loop.

You're likely familiar with the following but kindly review sections 8.3 and 10 of the .

Regards,

-Mamadou

Hi Mamadou,

can I share the layout modifications privately with you so you can check? thanks. 

Ernest

Hi Ernest,

Yes you share schematic + PCB layout privately. 

I have sent you a friend request where we can take it offline.

Regards,

-Mamadou

Hi,

I sent the files privately. Looking forward to your feedback on layout & schematic.

Ernest

Hi Mamadou,

We have confirmed that the issue cannot be linked to the HI and LI input signals exceeding the limits. We added a small fast Schottky PMEG2010BELD in parallel with HI VSS and LI VSS (< 1.5 mm away from LMG1205) and confirmed with an oscilloscope that both inputs are now within the appropriate range. Still, the issue persists with no change in frequency or behaviour. 

So it really looks like, either the level shifter of LMG1205 or the boostrap / active clamp circuit may be malfunctioning.

Note that during those cycles, the HS and HB become negative and transiently exceed the -5 V / 0 V limit. Could this cause a malfunction to the bootstrap or active clamp circuits?

Looking forward to your feedback on this and the design files I already sent privately!

Ernest

Hello Ernest,

I will review the schematic and get back before COB Tuesday.

Meanwhile with regards to the latest information, before I can comment on the level shifter, I need to rule out all the external signals exceeding abs max of the driver IC before I can assume the level shifter is behind the issue. Can you share insight into the duration at which HB-HS is exposed to ~-5V.

If HB_HS is consistently seeing -5V (abs max being 0V), the internal clamp circuitry might be getting stressed and clamping the gate high while the input stage has a low command. To rule this out, are you able to add an external clamp to maintain HB-HS within the recommended operating range to verify whether the issue still occurs?

Regards,

-Mamadou 

Hi Mamadou,

The time on which  HS is < -5 V (and can be up to -10 V) lasts always less than <20 ns. See the captures I sent before. After that transient, Then the voltage can remain at -2 V ~ -4 V (within LMG1205 recommended voltages) for a few 200 ns ~ 300 ns which corresponds to the drop of the low side transistor.

After that period of "normal behavior" within nominal ranges of HS and HB voltages, LMG1205 causes malfunction and activates the high side.

So current instead of decaying is increased again, and this is what at the end damages the power stage after a few milliseconds of massive power dissipation. 

As you recommend, I will check to add an external high power Schottky to clamp those negative voltages.

If the issue is related to the active clamp, would change the input inductor (L1) to 10 Ω ~ 47 Ω resistor help to reduce the stress? In normal operation, it will cause a small drop while in this "short-circuit" situation it would reduce the voltage at VDD and also the thermal power in the active clamp as confirmed by our simulation model. 

Hi Mamadou,

I have some interesting information: after adding a parallel Schottky PMEG10020ELRX to the low side transistor the problem disappears. Clearly, the problem is related to negative voltages on the HS pin.

The problem is that adding this Schottky adds extra capacitance and switching losses and we would prefer to avoid this on the final product, so the Schottky is a "patch" but does not work for us.

We definitively need some of your expert knowledge on how LMG1205 works internally. As you know, without the mentioned Schottky, the issue (oscillation and unwanted activation of HO) persists for several ms, even after the current has decayed and the HS voltage is > -3 V (within nominal range) so it should not be happening for such a long time. Could it be a thermal phenomenon inside LMG1205? Adding some extra information, the period of the re-activation of the high side decreases as bootstrap voltage increases. 

Hello Ernest,

Thanks for the updates.

The negative voltage on HS may be traced back to very high dv/dt on the falling edge of the high-side gate (based on the latest information and going back to the first waveforms you shared). The issue is consistent with applications with high dv/dt on HS causing negative transients that will impact the high side channel where HO output may exhibit a false logic.

This is commonly corrected by adding some turn-off gate resistors on the low-side and high-side to limit the dv/dt on the phase which will consequently reduce the negative voltage seen by the internal clamp and high-side internal pulldown transistor on HOL. The obvious trade-off is the increased switching losses of the FETs resulting from slowing down the rise/fall times at the gate.  

Alternatively, LMG1210 offers higher dv/dt capability and wider negative voltage margin of the HS pin to prevent HO from going high.

Regards,

-Mamadou