LMR36520: LMR36520ADDAR layout for EMI reduction

Bob,

The images did not attach properly. Please attach images and I'll take a look.

-Sam

Bob,

I should have asked this before but what frequency band are you seeing the issue? Can you attach an EMI plot?

If the issue is with higher frequencies >30MHz:

The input capacitors should connect directly to the GND plane with a direct connection to the PGND pin. C6 connects to GND through a via which adds lots of inductance. Try fly-wiring a wire from the GND pad of C6 to the PGND pin of the device. Same goes for C100.

The SW node copper looks to be bigger than necessary. Larger surface area means more high-frequency (>30MHz) EMI. Move the inductor closer and reduce the surface are of the SW node to improve EMI.

It is also a good idea to remove the thermal reliefs on the pins with high current and quickly-changing currents like VIN, GND, and pads to CIN/COUT.

Another idea would be to rotate the inductor. Inductors will emit differently depending on if SW is connected to the beginning of the winding vs the end based on the construction of the inductor.

For low frequency EMI (<30MHz) you will need to look into more input capacitance or an EMI filter (I don't see one on the schematic).

-Sam

Hi Sam,

Thank you for providing us your feedback.

Attached are the EMI plots: one from top of U9 and the second one from top of L1.

Most of issues I see are at higher frequency than 30Mhz when measured from top of U9. But lower frequencies also exists when measured from top of L1.

I will make appropriate changes based on your recommendations and I will provide you the new layout for your review.

Best Regards,
Bob    

Bob,

Yes 255MHz sounds about right for the switch node ringing. The input capacitor input loop inductance (physical loop area/length/thickness...) is what determines the amount of energy in this band. Having a better connection from CIN to the VIN pin should help this.

Let me know when you have the updated charts.

-Sam

Hi Sam,

Attached is updated layout for your review.

Thanks,

Bob

Hi Sam,

Please see my response below:

• Sam => I'd recommend putting a GND via on the island/peninsula between C6 and C32.
• Bob => I don't see C32 capacitor. Are you referring to R32?
• Sam => It would also help if L1 can move closer to the IC to further reduce SW surface area
• Bob => Currently it's placed fairly closely (within 50 mil) but I will bring it closer providing it doesn't cause any assembly issues.
• Sam => Also consider placing an 0603 capacitor from VOUT to PGND directly above the PGND pin to help with VOUT noise
• Bob => Are you referring to use a 0.1uF capacitor for high frequency noise?
• Sam => You may also add a snubber placeholder from SW to GND in case emissions are still too high.
• Bob => What values do you recommend for RC snubber circuit? Is it ok to place the snubber circuit next to C7?

Also do you recommend to void out the GND pour underneath L1 to prevent switch noise penetrating the GND?

Thank you,

Bob

Thank you Sam for the clarification. Attached is the latest placement including the snubber circuit (R165 & C158) and VOUT bypass (C156).

Thank you Sam. I will proceed with changing the C156 location. 

My last question is does it help to use an inductor with smaller form factor to reduce SW loop area?

Best Regards,

Bob

Hi Sam,

I am sorry but I forgot to include the snubber circuit schematic for you to review.

Please confirm snubber circuit is connected correctly.

Thanks,

Bob

Thank you Sam! I will keep you informed on EMI improvements once we do a new layout.

Bob