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Hi,
We are seeing EMI issue with LMR36520ADDAR. The layout used is very close to recommended layout in the datasheet.
Following is the schematic, placement and the layout of the part.
Please advice if you see issue with the design and how to improve EMI.
Thanks,
Bob
Bob,
The images did not attach properly. Please attach images and I'll take a look.
-Sam
Bob,
I should have asked this before but what frequency band are you seeing the issue? Can you attach an EMI plot?
If the issue is with higher frequencies >30MHz:
The input capacitors should connect directly to the GND plane with a direct connection to the PGND pin. C6 connects to GND through a via which adds lots of inductance. Try fly-wiring a wire from the GND pad of C6 to the PGND pin of the device. Same goes for C100.
The SW node copper looks to be bigger than necessary. Larger surface area means more high-frequency (>30MHz) EMI. Move the inductor closer and reduce the surface are of the SW node to improve EMI.
It is also a good idea to remove the thermal reliefs on the pins with high current and quickly-changing currents like VIN, GND, and pads to CIN/COUT.
Another idea would be to rotate the inductor. Inductors will emit differently depending on if SW is connected to the beginning of the winding vs the end based on the construction of the inductor.
For low frequency EMI (<30MHz) you will need to look into more input capacitance or an EMI filter (I don't see one on the schematic).
-Sam
Hi Sam,
Thank you for providing us your feedback.
Attached are the EMI plots: one from top of U9 and the second one from top of L1.
Most of issues I see are at higher frequency than 30Mhz when measured from top of U9. But lower frequencies also exists when measured from top of L1.
I will make appropriate changes based on your recommendations and I will provide you the new layout for your review.
Bob,
Yes 255MHz sounds about right for the switch node ringing. The input capacitor input loop inductance (physical loop area/length/thickness...) is what determines the amount of energy in this band. Having a better connection from CIN to the VIN pin should help this.
Let me know when you have the updated charts.
-Sam
Bob,
Looks good.
-Sam
Hi Sam,
Please see my response below:
Also do you recommend to void out the GND pour underneath L1 to prevent switch noise penetrating the GND?
Thank you,
Bob
Bob,
My mistake, between C6 and R32.
Yes, 0.1uF will work to help the high-frequency noise.
10 ohms 0603 and 47pF 0603 not populated is good for a snubber placeholder.
-Sam
Bob,
Looks great. It looks like you added C156 for the high-frequency noise. It would be better to place it between the PGND pin of the IC and the inductor. Or just above C6. Somewhere around there wherever abides by the layout/assembly constraints. You could even shift C97/8/9 to the left if necessary.
Other than that it looks great!
-Sam
Thank you Sam. I will proceed with changing the C156 location.
My last question is does it help to use an inductor with smaller form factor to reduce SW loop area?
Best Regards,
Bob
Bob,
A smaller form factor (especially smaller height) will help reduce EMI emissions.
-Sam
Thank you Sam! I will keep you informed on EMI improvements once we do a new layout.
Bob