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UCC27282: how to manage dead time?

Part Number: UCC27282
Other Parts Discussed in Thread: LM5106, , LMG1210

Hello,

I'm working on a high seed driver for a full bridge topology, the device is a class D amp for ultrasonic application.

We build a first prototype with LM5106 driver wich include dead time management. We found LM5106 is not fast enough and some very small pulse can be skipped.

Then we get advice to look at UCC27282 which don't include dead time management but an interlock functionality.

We adress the driver with an analog part which generate our pwm train, so there is not dead time management here.

How can we manage cross conduction in this design ? We simulate with high speed mos and simulation give us no cross conduction but how to be sure of that ?

Our analog pwm generator give us a single signal (HI) then we use a high speed inverser gate to generate the signal LI, I'm not fan of traditional discrete pwm dead time made with lot of logics.

I initialy think that interlock function will garantie no cross conduction with a minimum dead time but as i understand datasheet interlock is not made for crossconduction issue.

I don't found other driver than LM5106 with dead time management but faster (something like 50ns dead time for example, maybe the lmg1210 but too expensive and no automotive)

  • Hello Briquel,

    I recall the previous conversation regarding using the LM5106, and the suggestion to consider the UCC27282.

    I understand that the PWM controller only generates the one PWM pulse for the high side signal. The configuration you have using an inverter to generate the low side driver input is a common solution but does have the concern you mention that the inverter and in this case the interlock on the gate driver inputs will not insert any deadtime between the high side and low side inputs.

    I would suggest making sure there is some dead time between the signals driving the MOSFET gate to source voltage. One way which maybe you have in place already, is to configure the gate drive network on the driver output to MOSFET gate, so that the turn on is slower than the turn off Vgs voltage. It is common to have higher gate resistance on the turn on path than the turn off path. This is usually with a turn on gate resistance with a parallel diode for the turn off path with lower or no resistance.

    Another method would be to have some small delay in the inverter path that delays slightly the signals to the LI pin to the HI pins with a one edge delay. I n this case you want the turn off edge to be no delay and a slight delay on the turn on (rising) edge.

    Confirm if this addresses your questions or you can post additional questions on this thread.

    Regards,

  • Hello Richard,

    I really appreciate you recall previous discussion about my fastbridge timing issue.

    As you understand I'm a beginner in mos driver and bridge and after reading your suggestion about adding resistor//diode on gate path I try again this approach with calculation this time and 'ho it works' :)

    So I can now adjust resistor value to fine tune dead time and can now exploit my super fast mosfet.

    I think will use only this way to generate deadtime, the inverser gate I use is super fast (ns delay) so this inserts a ns deadtime for the up front and overlap on the down front but the interlock logic take care of this small overlap.

    Thanks to recall me what is the basis on driver and mosfet bridge but help me to understand how to work within this topic.

    Regards,

    Florian Briquel

  • Hello Briquel,

    Thank you for acknowledging this addressed your questions and resolved your concerns. This helps us and the forum a lot.

    Regards,