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Original question:

UCC29002: UCC29002 Excel Calculator Tool in A Low Side Current Sense with V+ sensing only (No R_SENSE)

UCC29002: Saturation / Load-step issues

WB
Intellectual 350 points
Part Number: UCC29002
Other Parts Discussed in Thread: UCC28951, PMP8740

Hello,

In an earlier thread, I had questions about UCC29002/1 in no-Rsense and low-side configuration. I reference the thread here as the schematic and info are related.

https://e2e.ti.com/support/power-management/f/power-management-forum/972989/ucc29002-ucc29002-excel-calculator-tool-in-a-low-side-current-sense-with-v-sensing-only-no-r_sense/3609967?tisearch=e2e-sitesearch&keymatch=UCC29002#3609967

I built the system with three 600W PSFB Modules that have independent input source. The output of the three modules is combined to a 1800W/-48V DC bus. Each module uses UCC29002/1 load sharing controller.

Observations:

  • Saturation Issue Case 1:
    1. ALL three modules are powered up.
    2. Activate only one of two of the PSFB converter.
    3. Result: UCC29002/1 ADJ pin will saturate (7mA goes through Q2) on ONLY one of the UCC29002/1 controllers under no LOAD.
  • Saturation Issue Case 2:
    1. ALL three modules are powered up.
    2. Activate the PSFB converter modules before closing the output switch Q1.
    3. Result: UCC29002/1 ADJ pin will saturate (7mA goes through Q2) on ONLY one of the UCC29002/1 controllers under no LOAD.
  • Load Sharing Bus (LS) Issue:
    1. Two out of three modules are powered up
    2. Result: LS BUS seems to be held low unless the disconnect it from the non-powered-up module.
  • Regulation issue:
    1. All three modules are active.
    2. 1500W Load.
    3. The load is shared among all three modules with 3% error.
    4. Sometimes, after running the system for several minutes, one of the LS controllers will share half the current the other two modules do.
  • Load-step:
    1. All three modules are active.
    2. The maximum load can star-up with is 1200W, which is the maximum capacity of two modules out of three.

Questions:

  • Please advise what could cause observation 1 given that it happens 50% of the time and RADJ is carefully selected and has enough margined for regulation.
  • Please advise what could cause observation 2 and whether I should connect Radj after the output switch Q1.
  • Please advise regarding Observation 3. Is there any issue if:
    1. Only one or two of the three modules are powered-up > The LS pin on non-powered controller will see a maximum of 8V since the bus is shared. That goes into the absolute maximum rating of LS-PIN when the chip is not powered. If that is an issue, any suggestions?
    2. All modules are powered up but only one or two of the three modules PSFB Converter are active? Do I need to disable the LS controller if the module is powered up but the PSFB converter is not enabled? Suggestion?
  • Observation 4: What could cause one of the LS controllers to lose regulation?
  • Observation 5 could be due enabling LS at the startup circuit on UCC29002-1. I am planning to test with UCC29002 but I am not sure about one statement in the datasheet: “Both the load share driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the average per module current level represented by the LS bus voltage”. Does that mean output current has to reach 80% of the maximum load current for the controller to revert to normal? What if the load is dynamic (i.e., 25% only)?

 Thanks

  • +1
    TI__Genius 9140 points

    Hi WB,

    it looks like the system still do not works stable with  current share controller.

    does the parameter in the schematic match the value you use in the real system?

    I check your schematic again, and found you use a very small Acsa(in your schematic only 30k/10k=3). The output of amplifier is too small.

    you can change R10/12 to 1kohm, R8/14  to 100k, C6/C9 to 47pF or 56pF.

    and see whether the system still cannot stable especial with your condition 4(regulation issue)

    I double confirm

  • 0 in reply to David Huang33
    Intellectual 350 points

    Hi David,

    The gain on the new design is already set to 100. The main (current loop) is stable with 2.4KHz cross over frequency, >30dB gain margin, and > 68 degree phase margin. I have attached the updated schematic. 

    Please advise your feedback on each of the five questions!

    Thx

  • 0 in reply to David Huang33
    Intellectual 350 points

    Marked solved by mistake. Can you please remove the marker? 

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB,

    no worry about the marker, when you answer the post again, the post will be activated again.

    thanks for the new schematic.

    I would like to offer feedback to your questions one by one only when we can make sure you have a correct design of the controller.

    from your schematic, I am wondering why the Radj is 0ohm? it will let the controller saturation.

    another suggestion is you can remove the D20 to see whether it improves. I am worried that the leakage current  of the Diode may influence the system.

    I already added the calculator with Mathcad version in your previous post, you can also download from TI website by yourself.

    My suggestion is you can add all the system parameter in the calculator, then if you have any parameter that do not match your schematic, we can discuss further.

    thanks.

  • 0 in reply to WB
    Intellectual 350 points

    David,

    Here is the latest update:

    - Moving the feedback loop (also the Adjust point for the LS) to +VOUT (After the output FET) helped in solving the first four issues. The load-step issue was found to be caused by a transient in the transformer primary due to the magnetization inductance. Solved by adjusting the CS filter. 

    Not sure why the output FET (reverse current protection) is causing imbalance and instability in the LS controller. The FET is TPH2R608NH,L1Q, Rdson: 2.6mOhm. The LS controller will start to act when the current on each of the 3 module is around 8.5A. The voltage drop across the FET@8A is around 25mV.

    # Any reason that could cause an imbalance and instability on one of the modules?

    # I don't like to move the feedback loop after the switch (+VO > +VOUT), but I have no other solution for now. Do you see an issue given that one or two modules out of three could be turned off depending on the load condition?  

    # Give that the system could turn off one or two out of the three modules based on the load condition, is there problem with the LS BUS with some controllers with no 12V power supply?  Should the LS signal be disconnected or the controller disabled? 

    # The gain is set to 100. According to above calculations, the maximum gain can e set up to 160. Does increase the gain to 150 improve the accuracy? 

    # Finally, regarding UCC29002. The datasheet stats that: “Both the load share driver and the adjust amplifiers revert to normal operation as soon as the measured current exceeds 80% of the average per module current level represented by the LS bus voltage”. Does that mean output current has to reach 80% of the maximum load current for the controller to revert to normal? What if the load is dynamic (i.e., 25% only)?

    Thanks

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB,

    thanks for your quickly updating. By changing the adjusting voltage from (+VO to +VOUT helps a lot for the current share system.

    My guess it that the Rdson which equal to 2.6mohm, and the current sense resistor is only 5mohm, the Rdson account for 40% of the current sense that is too much. and the Rdson with different mosfet in each module is not match well, that may cause current share system oscillation.

    if we can reduce the Rdson for example to below 5% of the current sense resistor, I would expect by connecting VO+ should be also OK.

    You can increase gain, it should help on the accuracy, you can also increase the current loop bandwidth by decreasing the RC on the EA pin to help on the accuracy.

    once the module is turned off, then the supply of the UCC29002 is disabled, and the system surely can be stable.

    the 80% is average current not the maximum load current. it is activated at start up to help on quickly allow the system to have a better current share performance, and may cause a higher overshoot of the output voltage.

    at dynamic condition, it is already disabled.

    You can also select UCC29002-1 that already disable the function.

  • 0 in reply to David Huang33
    Intellectual 350 points

    Hi,

    Thanks for your feedback.

    It's not gonna be feasible to reduce Rdson to 0.25mohm without adding significant cost to the design. The only solution would be to move the sensing resistor to the high side and connect the controller across the sensing resistor and FET or use the FET Rdson as a sensing resistor but that is a major design change not mentioning the other issues with high side current sensing on 48V bus. I will move the connection to +VOUT. I just need to make sure that a high impedance 2.5V on the UCC28951 EA pin is not an issue when the chip is not powered up. Can you confirm this or I need to start different post to confirm it?

    "once the module is turned off, then the supply of the UCC29002 is disabled, and the system surely can be stable."

    What if the module is powered up but the UCC28951 is disabled (ideal mode)? Because I could have input power on all module and only one is driving the load. Do I need to disable the LS controller in this case? 

    One last question: What could cause the Load sharing to be stable in room temperature and one of the module starts to drop off (shares nothing) under 50C? All the R/C components in the design have 1% tolerance including the current sense resistor. 

    Thx 

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB:

    adding 2.5V on the EA- is not an issue with no VCC on UCC28951.

    Do not need to disable the LS controller since you already disable the UCC28951 and the modules that do not disable UCC28951 be the master module. Other modules that disable the UCC28951 will not be turning on at this condition. For the system setting, it is normal used.

    is it easy to reproduce the phenomenon at one fixed module or the sharing nothing is random?

    usually the current sense resistor uses 1-2 ppm level with temperature raising. can you confirm whether the unstable issue is from current sense resistor?

  • 0 in reply to David Huang33
    Intellectual 350 points

    Hi David,

    The phenomena of drop off or sharing way less current happen on one of the 3 modules that have the lowest output voltage. For instance: 48.12V, 48.35V, 48.22V. At the first run, all three modules will share 1500W (500W each) with an error of 2%. Once the ambient temperature rises to 50C, the first module will share nothing if the other two module can handle the load or share part of the load when the other two modules are fully loaded and the LS controller is saturated. 

    I was suspecting the BJT transistor on the Adj pin since it has non-linear characteristic that is temperature dependent.

    Another observation I found is that when I increased the gain to 150 instead of 100, the system became more sensitive to any temperature variations and the LS controllers less stable. Of course, when I changed the gain I did all the calculations again and adjusted the compensation network.

    The sensing resistors I have are two CRA2512-FZ-R010ELF in parallel. They have 1% tolerance and 75ppm/c. Not sure if they are the reason for instability under 50C. 

    By the way, if there a way to do a loop analysis for the LS controller when it's active?

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB,

    my mistake for the current sense resistor. <100ppm/c should be enough.

    can you change to other BJT to verify your analysis?

    if this is a current share loop issue, I would suggest you lower the bandwidth by increasing the RC on the ea to let the current share slowly to see whether any improvement at  50degree.

  • 0 in reply to David Huang33
    Intellectual 350 points

    Hi David,

    # Increasing the gain made the system even more sensitive to lose regulation and for the EAO to saturate when the total load reaches about 70%.

    # The LS Bus is very sensitive. The chip seems to fault when I try to use DMM to measure the voltage on PIN 7.     

    *** I was able to get the system to a stable point with 1% LS regulation after I had to:

    1) Reduce the gain to 50 (R59/R67=15K , R61/R63= 300Ohm, C52/C54=1.2nF).

    2) Change R64 to 1K ohm (Very essential to stabilize the system).

    3) I was also able to move back the feedback point to +VO instead of +VOUT after the above two changes.

    Here is a summary of my observations and understanding about this issue:

    A) Low-side current sense with no-Rsense and 48V is not a typical application for UCC29002/1. Add to it the electrical and magnetic noise in the PSFB PS topology. 

    B) When the current sense resistor is used on the Low-side, the ground reference loop for the LS BUS is not strongly coupled to the signal. The LS controller is referenced to -VO, which is not the common ground between all PS modules. What is common is the -VOUT, which is after the sensing resistor with 65mV drop across the sensing resistor!! The LS signal, daisy chained from one controller to another, will be very sensitive to any kind of noise even when you do the best layout consideration to route the signal in quite areas.  I can see ~100mV normally distributed noise on LS BUS. The noise increases as the load increases.

    C) Increasing the gain will increase system accuracy as you will have a wider dynamic range, but will also increase system sensitivity to noise and load transient. I found out that once UCC29002/1 saturate, it is hard to restore LS regulation unless the load is reduced to the limit of a single controller.

    D) The voltage limiter transistor and voltage reverse diode on Adj pin makes the system sensitive to temperature variations as the BJT transistor IC current is temperature dependent. The suggestion here is to use MOSFET with a Vgs(th) < 2V. Limit 48V to 12 will dissipate some heat on the transistor (~200mW MAX). The reverse voltage diode is very important to block the 12V-VCE from back feeding the output.     

    E) Adding 1Kohm resistor in series with the LS pin helps to damp some of the noise as well as reduce the effect of the reference ground miss-match. The value was experimentally identified. Larger values will cause LS not to work. Lower values will work but the LS error could be 5~8%. You need to find the sweet resistor value that keeps all LS controllers happy. Also the resistor significantly reduced the noise and touch sensitivity on the LS pin. 

    Please let me know your thoughts about each point as well. It's very important to understand the behavior as the product utilizing UCC29002/1 falls into the functional safety type applications...

    I hope that this post can help other engineers to diagnose the LS controller for similar application.

    I will close this after your feedback/. 

    Thanks

  • 0 in reply to WB
    TI__Guru**** 189401 points

    Hi, WB,

    David is out of the office. He'll be back later this week and reply to your last set of questions.

  • 0 in reply to David Huang33
    Intellectual 350 points

    David,

    I was reviewing a feedback I received from Colin last year. Please Check the note highlighted in green. In my current design, UCC28951 is referenced to 0V (before R_CS). Also, the feedback bottom resistor (R_Bot) is connected before R_CS.

    I am not sure what Colin meant by the green note!

    A) Did he mean to only connect R_Bot after R_CS?

    B) or all UCC28951 ground points should be referenced to VO- (after R_CS)?? This is not possible as all the PWM signals are referenced to the most negative point (0V).

    This is exactly what I have been chasing! 

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB,

    thanks for your detail summary of this post. it is useful for

    Can I ask one more question on your schematic?  I saw your schematic connects UCC29002 GND pin to -VO point which is the system terminal point. And from Colin's suggestion, UCC29002 GND should be connected to 0V(left side of current sense resistor) in your system. that is because if the UCC29002 gnd do not connected to the most negative voltage point, and the AMP in the UCC29002 will influenced by the voltage through the current sense resistor.

    I still do not know why we have a recommended resistor with 1k on LS line.

    My understand of the green you highlight from Colin is that he suggest both UCC28951 Ground and feedback bottom resistor connects to the VO- at the same time.  The aim is to lower the influence of voltage drop on current sense resistor.

  • +1 in reply to David Huang33
    Intellectual 350 points

    David/ -VO and -VOUT on my schematic is 0V and VO- on Colin's schematic, respectively. Therefore, UCC29002 GND does connect to the most negative point (-VO/before Rsense). The green text is not practical for a clear reasons. I was hopping to get your thoughts about each point I listed in the summary.

    I believe that UCC29002 has never been tested or evaluated in similar configuration and application. The chip can do the trick in case of low voltage DC/DC converters, but not high voltage resonance converters. Take PMP8740 for example; UCC29002 was placed on the design layout but cleaned out from the schematic for a reason (properly didn't work as intended).

    Please feel free to close this post.

  • 0 in reply to WB
    TI__Genius 9140 points

    Hi WB,

    I do not know the history of PMP8740, so I do not know why there is ucc29002 in the layout but not in the schematic.

     I am supporting another case with also high voltage output(48V), and still under debug. From the datasheet and the application note that we can get from TI website, there is no evidence that the controller can not support this kind of application. I will update it to you since you already add me in the forum as friendship.

    thanks for your sharing of your debug. I believe it should be helpful for other engineer.