TPS2372: Please help to check the schematic and layout.

Hi User,

I will take a look & give comment this week.

Thanks,
Tom Amlee
PoE PD Apps Engineer

Hi User,

This looks like a newer version of a previous schematic I've reviewed for you: e2e.ti.com/.../773670

The first 2 comments were satisified.
Regarding the last comment: using the output of the 10V series regulator (MAX5974D_VC_PD) should work for pulling up the optocoupler, but I would caution that will result in additional current & losses through the regulator. Using Vdd may be more simple, but it's up to you.

Regards,
Tom Amlee
PoE PD Apps Engineers

Also, the input bulk capacitors PC174, PC175, PC154, PC169 are 39uF instead of 47uF. If it does not work as intended, then consider switching back, otherwise, you may be fine.

Thanks,
Tom Amlee
PoE PD Apps Engineer

Hi Thomas,

Thank you for your reply.

Could you kindly help to check the layout?

Hi User,

I will certainly check layout. I noticed you posted a separate thread for the same design (e2e.ti.com/.../780206), so I will paste your question below & address in this thread.

Regards,
Tom Amlee
PoE PD Apps Engineer

"For this design, we concern that:

1) The increase of current through each optocoupler’s LED to a minimum of 3mA at the lowest input voltage.
- Concern about the increase in system power dissipation due to the increase in optocoupler LED current for PD17, PD32, PD33 and PD13, PD15, PD16.
- The TPS2372 datasheet’s recommended operating conditions for TPH, TPL and BT sinking current is 3 mA maximum (10 mA absolute max).

Unlike the TPS2373, the TPS2372 does not have a low voltage output to power the opto LEDs. But it may be possible to use the MAX5974D_VC_PD voltage that is developed from the tertiary winding of the power transformer (T3) for the PWM controller (PU11). The voltage at MAX5974D_VC_PD will remain somewhat constant over the 42.5 to 57V input range, and its value will be much lower. Therefore it would be possible to provide 3 mA to each opto LED without the large increase in system power dissipation.

Could you help to check this design is ok or not?"

5468.95_2213T00_035_20190226-1700-163.brd

4530.5428.TPS2372.pdf

Hi User,

Regarding the note about the optocoupler pullup: I did not see that the output of the bias winding & the series linear regulator were the same net. That should be fine.

My only comment on layout is to be sure that the ground return path from PC112/PC124 to the terminations of the current sense resistors PR144/PR71 is as short as possible. Overall, the major power paths are tight & well optimized.

Thanks,

Tom Amlee

PoE PD Apps Engineer