TPS650864: Kindly Review the Schematic of TPS6508641 for timing attached for MPSOC Schematic Design

Hi Shyam Daram,

I am looking over your schematic and will get back with you tomorrow.

Thank you for your patience,

Layne J

Thanks very much for your detailed points

In precise i want the timing / sequence to be verified

Kindly also verify the sequence, will the PMIC perform the sequence provided ?

the have verified it from Xilinx side for sequence

Waiting for your Response

PS: i have made the changes proposed for SCH

1. As Suggested, shall i replace the 22uF capacitors i have placed at output of 1/2/6 Bucks with a 100uF ? , kindly suggest the type also , shall i go with a Tantalum type or a MLCC ?

2. Please Mention the formula to calculate the output voltage of Buck 1

3. Also please review the upper schematic portion which is  TPS544B25, where it is responsible for generating 0.72V to core supply for a maximum current requirement not exceeding 20A

I have attached the reference that i generated from WEBENCH tool, i have tried to straight away use the design provided by WEBENCH, still i would like to take your second opinion

WBDesign136.pdf

Thanks

Thanks for your timely answers

1. Thanks for the info i shall update my SCH for it

2. please provide the reference for this in datasheet, unfortunately i could not find it directly in any page, please provide page number / recommended feed back resistors

3. i have put a alternate thread for this  kindly mark concerned engineer to it

4. Apart from this if you see the schematic i am not using Buck5, how to terminate un used buck, can i follow the same as done for LDO?, connecting output with a capacitor and leaving feed back path floating, kindly suggest.

5. What is the need of 0201 shorts referred as Z in the schematic, i have took it as a reference from Ultra96

Layne J said:

4. For this part number you must populate BUCK5 circuitry. BUCK5 Power Good is used to sequence BUCK6 and if BUCK5 is not populated the device will power fault and restart. If you would like to not use BUCK5 you can switch to TPS650861, which is the user programmable version of the TPS650864x devices. The distributor Arrow can also provide pre-programmed units.

Layne J

At this crucial point of time, it will be difficult for me to change the PMIC, just because of one Buck not being used

is having load compulsory ? or can i leave as shown in schematic but not floating

In fact i am using the PMIC in always on mode if you see the SCH , does your statement valid for this too ?

Kindly suggest an alternate way to make Buck 5 reach its PGOOD

Hi Shyam Daram,

Yes it is required to have BUCK5 reach PGOOD, even in always on mode. TPS650861 is the exact same PMIC as TPS6508641. It is pin to pin compatible and the same silicon, however it allows for the user to program it to fit their needs. If changing to TPS650861 is not possible, you do not need to put any load on BUCK5 for PGOOD on BUCK5 to go high. 

Alternatively, you could switch what BUCK3 and BUCK5 are connected to. In this case you can depopulate BUCK3 circuitry and connect BUCK3 feedback pin (FB3) to the output of BUCK5. This will cause the device to think that BUCK3 has reached output voltage and cause PGOOD for BUCK3 to go high. This works because BUCK3 and BUCK5 are set to use the same output voltage. You need to switch BUCK3 and BUCK5 because BUCK5 sequences before BUCK3. 

Best regards, 

Layne J

Layne J said:

Hi Shyam Daram,

Yes it is required to have BUCK5 reach PGOOD, even in always on mode. TPS650861 is the exact same PMIC as TPS6508641. It is pin to pin compatible and the same silicon, however it allows for the user to program it to fit their needs. If changing to TPS650861 is not possible, you do not need to put any load on BUCK5 for PGOOD on BUCK5 to go high. 

Alternatively, you could switch what BUCK3 and BUCK5 are connected to. In this case you can depopulate BUCK3 circuitry and connect BUCK3 feedback pin (FB3) to the output of BUCK5. This will cause the device to think that BUCK3 has reached output voltage and cause PGOOD for BUCK3 to go high. This works because BUCK3 and BUCK5 are set to use the same output voltage. You need to switch BUCK3 and BUCK5 because BUCK5 sequences before BUCK3. 

Best regards, 

Layne J

I have took the decision of powering the DDR IC rails with Buck5

VCCO or the 1.2v of IO lines supply for FPGA will be taken care by Buck3

This solved my problem

More over i have few more doubts

1. Kindly provide Errata of the device , as i want to see any known problems before launching for layout

2. Also total power dissipation or power consumption calculation of overall IC are required, do i need to use any heatsink if operate the device for worst case temperature of 55 degree centigrade ?

3. Is there any worst case estimation tool for the device ?

Hi Shyam Daram,

I am looking into your questions and will have an answer for you shortly.

Best regards,

Layne J

Layne J said:

Hi Shyam Daram,

I am looking into your questions and will have an answer for you shortly.

Best regards,

Layne J

Waiting for response

Hi Shyam Daram,

Apologies for the delay. There is not Errata or worst case estimation tool for this device. We do have a power estimation tool that I will share shortly. 

Best regards,

Layne J

Thanks Very much, i have few points to say

1.  Estimation Seems to fail When Buck 4 output is 3.3V, my schematic strictly follows this

2. Input for 3,4,5 is ok if it is 5V ? or it should be 5.3 ? as default values entered are 5.3 previously

3. Are On trace test points preferable ? i want to save some space , i want test points for all rails of PMIC, kindly suggest any layout guideline

4. Attached is the Latest Schematic with replacing the 0.72 source(TPS544B25), as at this thread TI has said the device is not compatible for 0.72 Generation, so i have switched to using a TPS548B22

Kindly re-look at latest Schematic, i have done all previous changes proposed by you

Hi Shyam Daram,

1. I found a small bug in the back end logic for this spreadsheet. I want to verify my solution for this issue and will post an updated version tomorrow.

2. Yes a 5V input for those rails is fine. 

3. What rails are wanting to place test points on? Generally it is up to you for where you would like to place the test points. I would recommend reviewing the reference design using this part, TIDA-01393. Link to the design here.

4. I will review the schematic soon and give my feedback.

Best regards,

Layne J

Thanks for the update, i have used it and found my worst case consumption would read to Maximum of 20W at an ambient 55dC

i have one last doubt, the datasheet of PMIC says it can source up to 7A from Buck1, 2, 6

I have made my design expecting Maximum worst case consumption of 5A from 1,2,6. The FET which is at the output of the Buck1,2,6 is also good and supports up to 15A

is there any Disclaimer of using Buck 1,2,6 to their worst scenarios ?

PS: even the beads i have selected in order to provide noise filtering/ cutting off the rail are infact 100ohm Impedance @ 100Mhz