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[FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 / AM62L - Supported bootmode configurations

Kallikuppa Sreenivasa
Guru**** 211600 points

Part Number: AM62L
Other Parts Discussed in Thread: AM62D-Q1, AM625, AM623, AM620-Q1, TMDS64EVM

Tool/software:

Hi TI experts

help me understand the supported bootmode configurations for the below family of processors

AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 / AM62L

 RE: [FAQ] TDA4VH-Q1: Achieving Functional Safety with Boot 

  • 0
    TI__Guru**** 211600 points

    Hi Board designers,

    Please refer below inputs for AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 family of processors.

    AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 supports Full pin count (x16) bootmode configurations.

     https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1391522/faq-am625-am623-am620-q1-am64x-am243x-am62ax-am62px-am62d-q1-am62l---bootmode-implementation-without-isolation-buffers 

    When bootmode buffers are not used, the bootmode configuration resistors can be connected directly to  the SOC bootmode inputs.

    SOC bootmode input pins can be configured for alternate functions.

    When configured for alternate functions after boot, the recommendation is to connect to the alternate function through a 0R series resistor to be able to isolate to test the boormode functionality as required.

    For addition information, refer to processor specific data sheet, TRM, Hardware design considerations user's guide and schematic design guidelines and schematic review checklist user's guide on the processor sepcific product page.

    Example:

    https://www.ti.com/product/AM625


    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1414148/faq-am625-am623-am620-q1-am64x-am243x-am62ax-am62px-am62d-q1-am62l---bootmode-implementation-with-isolation-buffers-used

    Regards,

    Sreenivasa

  • +1 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 211600 points

    Hi Board designers,

    Please refer below inputs for AM62L

    5.3 Boot Process

    Boot Process Flow

    Boot Mode Pins

    BOOTMODE Pin Mapping (Full Pincount)

    Primary Boot Mode Selection and Configuration

    Backup Boot Mode Selection and Configuration

    AM62L supports Reduced pin count (x4 pins) bootmode and Full pin count (x16) bootmode configurations.

    BOOTMODE Pin Mapping (Reduced Pincount)

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 211600 points

    Hi Board designers,

    When Full pin count boot functionality is required with low pin count boot mode configuration, the low pin count mode provides configurations that can read the boot configurations programmed to eFuse.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 211600 points

    Hi Board designers, 

     Usage of BOOTMODE[8] in DEV BOOT mode

    (+) AM6442: Usage of BOOTMODE[8] in DEV BOOT mode - Processors forum - Processors - TI E2E support forums

    I was trying to boot a (custom) AM64x in DEV BOOT mode and initialize it using CCS, an XDS110 and the load_dmsc_hs_fs.js from MCU+ SDK 11.00, and that constantly failed. Trying the same on a TMDS64EVM worked just fine.

    I manually went through the steps performed by the load_dmsc_hs_fs.js script and noticed that the R5f was in a slightly different state on the custom board.

    On the custom board, the R5f was always in Thumb mode, and "Thumb exception enable" bit (TE) in the system control register (SCTLR) was set. After clearing Thumb mode back to ARM mode and with a breakpoint on the entry point I was able to manually load the sciclient_ccs_init.release.out binary on the custom board, too.

    It took me a while to realize that the difference was due to the state of the BOOTMODE[8] pin. With BOOTMODE[8] high, the EVM behaves the same, i.e. the R5f comes up in Thumb mode, and the load_dmsc_hs_fs.js script fails. After switching BOOTMODE[8] to low, the script succeeded on the custom board, too.

    According to the TRM, BOOTMODE[8] is reserved in DEV BOOT mode, and reserved/unused pins should be pulled high or low, but not floating, i.e. as if they're "don't care". It seems that isn't true for BOOTMODE[8] in DEV BOOT mode.

    Is this expected behavior? Is this documented somewhere, and I just missed it? Can you explain how that pin is used in DEV BOOT mode? Is there any other functionality behind that pin, or merely a non-useful reset value for TEINIT (which sets the default for SCTRL.TE, which would explain why the core comes up in Thumb mode)?

    Yes, the above observation is correct. For most of the boot modes the Bootmode[8] pin is reserved and can be pull up/down. But for Dev/NO Boot mode this pin defines the mode of the CPU whether to operate in ARM or Thumb mode.

    When the B8 pin is high the mode of operation is Thumb mode and while low the mode of operation is ARM. You will need to set the mode of operation to be ARM (B8 pin pull down) in order to run the sciclient_ccs_init.out binary successfully.

    Regards,

    Sreenivasa