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DRA821U: Please check if SERDES0_REFCLK outputs 2Ghz clock which connected to PCIe REFCLK without Clock Generator

Jack
Mastermind 9105 points
Part Number: DRA821U

Hi 

There's a question that customer wants to clarify about SERDES0_REFCLK.

It seems the SERDES0_REFCLK ports can be bi-directional clock I/O pins which can be used for SGMII, PCIe and USB3.0.

From my initial review, I am able to find the CLK SEL register for SERDES0_REFCLK as below.

I supposed the refclk port can be configured as output with the selected internally routed clock source.

However I can not figure out the maximum output clock speed at SERDES0_REFCLK port if external clock generator is not mandatory.

Could you please clarify whether the SERDES0_REFCLK (output) port is able to connected to PCIe' REFCLK without a Clock Generator device such like  PI6CFGL201BZDIE.?

If the use case above mentioned is allowed, please also clarify whether the serdes0_refclk can output up to 2Ghz 

Customer supposed the clock speed can be sufficient with 2GHz for PCIe.

Thanks.

  • 0
    Mastermind 9105 points

    Hi 

    As I checked AM64x_GP_EVM_User Guide, I could find the similar use case as SERDES_REFCLK (output) is connected to PCIe Connector. 
    For this use case, The user guide said the PCIe reference clock to the SoC will be provided by PCIe slot connector when processor is configured as downstream port and PCIe reference clock from SoC(SERDES0_REFCLK0) will be provided to PCIe slot connector during root complex mode of operation.

    If the same approach can be applicable to DRA821U as well, Could you please give more explanation especially about downstream and root complex mode as well? And also clarify the maximum clock speed of SERDES0_REFCLK output to PCIe if the use case is possible. Is it allowed up to 2Ghz over?

    Thanks

  • +1 in reply to Jack
    TI__Guru 52065 points

    SERDES_REFCLK can be configured as an output clock.  I do not know the fastest clock the IO can output.  However, for PCIe - while the data may operate up to 2GHz, the PCIe reference clock remains at 100MHz.  Can you clarify why you need to SERDES_REFCLK to operate at 2GHz?

  • 0 in reply to Robert Eschler
    Mastermind 9105 points

    Hi Robert

    Thanks for your kind answer.

    Regarding 2Ghz, it would be regarded with data transfer rate....I found it's mentioned on TRM. it's upto 8Gbps per lane. 

    PCIE reference clock is 100MHz as you said. 

    Thanks for clarification.