• State Answer Suggested
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 101 subscribers
  • Views 295 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5746: Sharing I/O Functions

RJ
Intellectual 2550 points
Part Number: AM5746
Other Parts Discussed in Thread: TPS659037

Hi Team,

Working on the AM5746/8/9 design and I/O. We need to investigate the sharing of I/O functions between Sitara Cores.

 We have a question for TI on using a single SPI port with two (2) Chip-selects (CS) to communicate to two (2) external slave devices. The SPI master would be the Sitara uP. But one slave device communicates with the Sitara DSP core while the other slave device communicates to the Sitara Arm A15 core. Is this allowed?

 -Can this be done by setting up DMA transfers where for each slave has allocated a separate Buffer (in Sitara Memory space), then the DSP core has access to one buffer while the A15 core has access to the other buffer?

 -Can this be done thru the Sitara switch matrixes?

  • 0
    TI__Intellectual 2550 points

    Follow up questions:

    1. Sharing of I/O ports between cores
      1. We have a question for TI on using a single SPI port with two (2) Chip-selects (CS) to communicate to two (2) external slave devices. The SPI master would be the Sitara uP. But one slave device communicates with the Sitara DSP core while the other slave device communicates to the Sitara Arm A15 core. Is this allowed?
      2. Can this be done by setting up DMA transfers where for each slave has allocated a separate Buffer (in Sitara Memory space), then the DSP core has access to one buffer while the A15 core has access to the other buffer?
      3. Can this be done thru the Sitara switch matrixes?
    2. TPS659037 - still is the suggested PMIC for the AM574x series?
    3. Powering and Power estimates – Questions on documentation
      1. The Doc: SPRAC79–March 2017 is for the AM572x (AM572X Power Consumption Summary) – Does it also pertain to the AM574x?
      2. The Doc: TIDUAV2A -  This document (page 5, near figure 3) has a link to SLIU011B (but link is broken). Please provide document for this link?
    1. From Data Sheet: The TPS659037 User’s Guide to Power AM572x and AM571x (SLIU011B) describes these connections, as well as the OTP settings of the two different PMIC configurations.
  • 0 in reply to RJ
    TI__Guru 54352 points

    Ramon,

    1. I'll defer to our SW team on this one.  

    2. Yes, that PMIC is recommended. Refer to the Schematic checklist for pointers:

    https://www.ti.com/lit/an/sprack7b/sprack7b.pdf?ts=1621289871110

    3. These are the relevant docs:

    https://www.ti.com/lit/an/spracl6/spracl6.pdf?ts=1621289875677

    https://www.ti.com/lit/ug/sliu011f/sliu011f.pdf

    Regards,

    Kyle

  • 0 in reply to kcastille
    TI__Guru 50045 points

    Ramon,

    In Processor SDK, our SPI driver doesn't support having 2x SPI drivers to access the same SPI port even with different CS.

    You can consider 2 options.

    1. Use 2 different SPI ports. A15 and DSP can control each SPI port independently.

    2. Use one SPI port with 2x CS. One SPI driver on A15 and use IPC to share data with DSP.

    Regards,
    Stanley

  • 0
    Intellectual 435 points

    Hi Ramon, KCastle and Stanley,

    Thank you for your follow up answers. The power documents provided are what I needed.  The SPI port restriction makes sense. 

    The last question the list is using DMA to move data from Core to memory and then from Memory to a I/O Port and vise-versa. Is this typically supported and if so, can you point me to documentation? 

  • 0 in reply to Eric Mac
    TI__Expert 6870 points

    Hi,

    Eric Mac said:
    using DMA to move data from Core to memory and then from Memory to a I/O Port and vise-versa.

    Yes it is supported. You can take a look at AM54x TRM section 17.2 - EDMA. And you can also take the reference from Mcasp deviceloopback example present at below path in the PDK: pdk_am57xx_1_0_17\packages\ti\drv\mcasp\example\.