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TMS320C6678: Power consumption spread sheet

Koichiro Tashiro
Mastermind 22945 points

Part Number: TMS320C6678

Hi,

My customer wants to estimate power consumption for C6678.
He refers to below spread sheet and document.
https://www.tij.co.jp/jp/lit/zip/sprm545
https://www.ti.com/lit/an/sprabi5b/sprabi5b.pdf

Customer wants to estimate "% Signal Processing (SP) Utilization" as accurate as possible.
Are there any methods or tools available?
For example, CCS tool to monitor %SP or benchmark program for SP X %, etc.?

Thanks and regards,
Koichiro Tashiro

  • 0
    TI__Mastermind 25535 points

    Dear Customer,

    Apologies for the delayed response and thanks for your patience. 

    Are you asking for something like LABVIEW connecting to CCS?

    Check whether the graph properties of CCS can fulfill your needs. For more info, visit
    https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_debug-graphs.html#

    Regards

    Shankari

  • 0 in reply to Shankari G
    TI__Mastermind 22945 points

    Hi Shankari,

    My customer wants to know how to estimate below parameter as accurate as possible.
    Here is quote from https://www.ti.com/lit/an/sprabi5b/sprabi5b.pdf

    "% Signal Processing (SP) Utilization is used to represent scenarios with high levels of CorePac activity. This corresponds to the case in which all eight instructions fetched by the CorePac are executed in parallel each for CorePac clock cycle, resulting in all eight functional units being active every cycle. Few CorePac algorithms will achieve 100% CorePac utilization because this requires execution of all eight function units every cycle with no stalls. Even intense applications do not spend all of the time executing such highly parallel code."

    Do you mean the CCS graph property can display this parameter?
    I could not find such information from users guide.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Mastermind 25535 points

    Hi Koichiro Tashiro,

    Let me forward your query to some of our experts and get back.

    Regards

    Shankari

  • 0 in reply to Koichiro Tashiro
    TI__Guru* 85935 points

    Hello Tashiro-san

    There are no modeling tools in CCS or otherwise for customer to look at how to feed %Signal processing vs % control code in to Power Estimation Tools. Customer will need to use their best judgement on this assessing how DSP is utilized in the system. 

    The c66x is a very efficient parallel architecture , but even with the most optimized codecs etc the instruction per cycle (IPC) is typical 4 out 8 or lower. Code optimized fir/fft routines written in assembly may hit in IPC of 6.  

    So best would be to for them to identify how much time DSP sends doing something that is signal processing intensive vs control loops or waiting for data etc for their their highest performing or most used kernels and then for the signal processing utilization typically use 50% as the upper bound for an IPC of 4 ( max instructions per cycle is 8). If they want to guardband further they can use 70-80% instead of 50%.


    Hope this helps

    Regards

    Mukul