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AM3359: Starterware AM3358 UART1, UART2, UART3, UART4 And UART5

Shubhakara P S
Prodigy 240 points

Part Number: AM3359

Hello Support@ti,

I am planning to use UART1, 2, 3, 4 and 5 on BeagleboneBlack AM3359 , But i am not getting any output on any of the UART's.

Here for your reference I have attached my code snippet kindly let me know if there any mistakes in my code.

File :- C:\ti\AM335X_StarterWare_02_00_01_01\platform\beaglebone/uart.c

/**
* \file uart.c
*/


#include "hw_control_AM335x.h"
#include "soc_AM335x.h"
#include "hw_cm_wkup.h"
#include "hw_cm_per.h"
#include "beaglebone.h"
#include "hw_types.h"

/**
* \brief This function selects the UART pins for use. The UART pins
* are multiplexed with pins of other peripherals in the SoC
*
* \param instanceNum The instance number of the UART to be used.
*
* \return None.
*
* \note This pin multiplexing depends on the profile in which the EVM
* is configured.
*/
void UARTPinMuxSetup(unsigned int instanceNum)
{
if(0 == instanceNum)
{
/* UART0 RXD */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(0)) =
(CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL |
CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE);

/* UART0 TXD */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) =
CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL;
}
else if(1 == instanceNum)
{
/* RXD */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(1)) =
(CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL |
CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE);

/* TXD */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) =
CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL;
}
}

/*
** This function enables the system L3 and system L4_WKUP clocks.
** This also enables the clocks for UART0 instance.
*/

void UART0ModuleClkConfig(void)
{
/* Configuring L3 Interface Clocks. */

/* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |=
CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_MODULEMODE));

/* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE));

/* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |=
CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

/* Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKTRCTRL));

/* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));

/* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |=
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL));

/* Checking fields for necessary values. */

/* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */
while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_IDLEST));

/*
** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the
** desired value.
*/
while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_IDLEST));

/*
** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to
** attain the desired value.
*/
while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

/*
** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
** register to attain the desired value.
*/
while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));

/*
** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register
** to attain the desired value.
*/
while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK !=
(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));


/* Configuring registers related to Wake-Up region. */

/* Writing to MODULEMODE field of CM_WKUP_CONTROL_CLKCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) |=
CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE;

/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_MODULEMODE));

/* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) |=
CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKTRCTRL));

/* Writing to CLKTRCTRL field of CM_L3_AON_CLKSTCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) |=
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

/*Waiting for CLKTRCTRL field to reflect the written value. */
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL));

/* Writing to MODULEMODE field of CM_WKUP_UART0_CLKCTRL register. */
HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) |=
CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE;

/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
CM_WKUP_UART0_CLKCTRL_MODULEMODE));

/* Verifying if the other bits are set to required settings. */

/*
** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
CM_WKUP_CONTROL_CLKCTRL_IDLEST));

/*
** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));

/*
** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_L4WKUP_CLKCTRL) &
CM_WKUP_L4WKUP_CLKCTRL_IDLEST));

/*
** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
** to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));

/*
** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));

/*
** Waiting for CLKACTIVITY_UART0_GFCLK field in CM_WKUP_CLKSTCTRL
** register to attain desired value.
*/
while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK));

/*
** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
** desired value.
*/
while((CM_WKUP_UART0_CLKCTRL_IDLEST_FUNC <<
CM_WKUP_UART0_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
CM_WKUP_UART0_CLKCTRL_IDLEST));
}

/****************************** End of file *********************************/
void UART1ModuleClkConfig(void)
{
HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);

HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);

HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;

while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);


HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) |= CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE;


while((HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
CM_PER_UART1_CLKCTRL_MODULEMODE) != CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE);

while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));

while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK)));


/* Waiting for MODULEMODE field to reflect the written value. */
while(CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE !=
(HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
CM_PER_UART1_CLKCTRL_MODULEMODE));

/*
** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
** desired value.
*/
while((CM_PER_UART1_CLKCTRL_IDLEST_FUNC <<
CM_PER_UART1_CLKCTRL_IDLEST_SHIFT) !=
(HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
CM_PER_UART1_CLKCTRL_IDLEST));
}

///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

File :- C:\ti\AM335X_StarterWare_02_00_01_01\examples\beaglebone\uart/uartecho.c

/*
* Uart1.c
*
* Created on: May 18, 2021
* Author: Shubhakar
*/


#include "uart_irda_cir.h"
#include "soc_AM335x.h"
#include "interrupt.h"
#include "beaglebone.h"
#include "consoleUtils.h"
#include "hw_types.h"

/******************************************************************************
** INTERNAL MACRO DEFINITIONS
******************************************************************************/
#define BAUD_RATE_115200 (115200)
#define UART_MODULE_INPUT_CLK (48000000)

/*
** The number of data bytes to be transmitted to Transmit FIFO of UART
** per generation of the Transmit Empty interrupt. This can take a maximum
** value of TX Trigger Space which is 'TX FIFO size - TX Threshold Level'.
*/
#define NUM_TX_BYTES_PER_TRANS (56)

/******************************************************************************
** INTERNAL FUNCTION PROTOTYPES
******************************************************************************/
static void UartInterruptEnable(void);
static void UART1AINTCConfigure(void);
static void UartFIFOConfigure(void);
static void UartBaudRateSet(void);
static void UARTIsr(void);

/******************************************************************************
** GLOBAL VARIABLE DEFINITIONS
******************************************************************************/
unsigned char txArray[] = "StarterWare AM335X UART Interrupt application\r\n";

/* A flag used to signify the application to transmit data to UART TX FIFO. */
unsigned int txEmptyFlag = FALSE;

/*
** A variable which holds the number of bytes of the data block transmitted to
** UART TX FIFO until the current instant.
*/
unsigned int currNumTxBytes = 0;

/******************************************************************************
** FUNCTION DEFINITIONS
******************************************************************************/

int main()
{
unsigned int numByteChunks = 0;
unsigned int remainBytes = 0;
unsigned int bIndex = 0;

/* Configuring the system clocks for UART0 instance. */
UART1ModuleClkConfig();

/* Performing the Pin Multiplexing for UART0 instance. */
UARTPinMuxSetup(1);

/* Performing a module reset. */
UARTModuleReset(SOC_UART_1_REGS);

/* Performing FIFO configurations. */
UartFIFOConfigure();

/* Performing Baud Rate settings. */
UartBaudRateSet();

/* Switching to Configuration Mode B. */
UARTRegConfigModeEnable(SOC_UART_1_REGS, UART_REG_CONFIG_MODE_B);

/* Programming the Line Characteristics. */
UARTLineCharacConfig(SOC_UART_1_REGS,
(UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
UART_PARITY_NONE);

/* Disabling write access to Divisor Latches. */
UARTDivisorLatchDisable(SOC_UART_1_REGS);

/* Disabling Break Control. */
UARTBreakCtl(SOC_UART_1_REGS, UART_BREAK_COND_DISABLE);

/* Switching to UART16x operating mode. */
UARTOperatingModeSelect(SOC_UART_1_REGS, UART16x_OPER_MODE);

/* Select the console type based on compile time check */
ConsoleUtilsSetType(CONSOLE_UART);

/* Performing Interrupt configurations. */
UartInterruptEnable();
numByteChunks = (sizeof(txArray) - 1) / NUM_TX_BYTES_PER_TRANS;
remainBytes = (sizeof(txArray) - 1) % NUM_TX_BYTES_PER_TRANS;


#if 0
UARTFIFOWrite(SOC_UART_1_REGS, "Hello World",0x0B);
unsigned char recv_array[11] = {0}, tx_array[11] = {"Hello World"};

int i = 0;
for (i = 0; i < 11; i++){
UARTFIFOCharPut(SOC_UART_1_REGS, tx_array[i] );
recv_array[i] = UARTFIFOCharGet(SOC_UART_1_REGS);
}
#endif

#if 1

while(1)
{
/* This branch is entered if the transmission is not yet complete. */
if(TRUE == txEmptyFlag)
{
if(bIndex < numByteChunks)
{
/* Transmitting bytes in chunks of NUM_TX_BYTES_PER_TRANS. */
currNumTxBytes += UARTFIFOWrite(SOC_UART_1_REGS,
&txArray[currNumTxBytes],
NUM_TX_BYTES_PER_TRANS);

bIndex++;
}

else
{
/* Transmitting remaining data from the data block. */
currNumTxBytes += UARTFIFOWrite(SOC_UART_1_REGS,
&txArray[currNumTxBytes],
remainBytes);
}

txEmptyFlag = FALSE;

/*
** Re-enables the Transmit Interrupt. This interrupt
** was disabled in the Transmit section of the UART ISR.
*/
UARTIntEnable(SOC_UART_1_REGS, UART_INT_THR);

}
}

#endif
}

/*
** A wrapper function performing FIFO configurations.
*/

static void UartFIFOConfigure(void)
{
unsigned int fifoConfig = 0;

/*
** - Transmit Trigger Level Granularity is 4
** - Receiver Trigger Level Granularity is 1
** - Transmit FIFO Space Setting is 56. Hence TX Trigger level
** is 8 (64 - 56). The TX FIFO size is 64 bytes.
** - The Receiver Trigger Level is 1.
** - Clear the Transmit FIFO.
** - Clear the Receiver FIFO.
** - DMA Mode enabling shall happen through SCR register.
** - DMA Mode 0 is enabled. DMA Mode 0 corresponds to No
** DMA Mode. Effectively DMA Mode is disabled.
*/
fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_4,
UART_TRIG_LVL_GRANULARITY_1,
UART_FCR_TX_TRIG_LVL_56,
1,
1,
1,
UART_DMA_EN_PATH_SCR,
UART_DMA_MODE_0_ENABLE);

/* Configuring the FIFO settings. */
UARTFIFOConfig(SOC_UART_1_REGS, fifoConfig);
}

/*
** A wrapper function performing Baud Rate settings.
*/

static void UartBaudRateSet(void)
{
unsigned int divisorValue = 0;

/* Computing the Divisor Value. */
divisorValue = UARTDivisorValCompute(UART_MODULE_INPUT_CLK,
BAUD_RATE_115200,
UART16x_OPER_MODE,
UART_MIR_OVERSAMPLING_RATE_42);

/* Programming the Divisor Latches. */
UARTDivisorLatchWrite(SOC_UART_1_REGS, divisorValue);
}

/*
** A wrapper function performing Interrupt configurations.
*/

static void UartInterruptEnable(void)
{
/* Enabling IRQ in CPSR of ARM processor. */
IntMasterIRQEnable();

/* Configuring AINTC to receive UART0 interrupts. */
UART1AINTCConfigure();

/* Enabling the specified UART interrupts. */
UARTIntEnable(SOC_UART_1_REGS, (UART_INT_LINE_STAT | UART_INT_THR |
UART_INT_RHR_CTI));
// UARTIsr();
}

/*
** Interrupt Service Routine for UART.
*/

static void UARTIsr(void)
{
unsigned int rxErrorType = 0;
unsigned char rxByte = 0;
unsigned int intId = 0;
unsigned int idx = 0;

/* Checking ths source of UART interrupt. */
intId = UARTIntIdentityGet(SOC_UART_1_REGS);

switch(intId)
{
case UART_INTID_TX_THRES_REACH:

/*
** Checking if the entire transmisssion is complete. If this
** condition fails, then the entire transmission has been completed.
*/
if(currNumTxBytes < (sizeof(txArray) - 1))
{
txEmptyFlag = TRUE;
}

/*
** Disable the THR interrupt. This has to be done even if the
** transmission is not complete so as to prevent the Transmit
** empty interrupt to be continuously generated.
*/
UARTIntDisable(SOC_UART_1_REGS, UART_INT_THR);

break;

case UART_INTID_RX_THRES_REACH:
rxByte = UARTCharGetNonBlocking(SOC_UART_1_REGS);
UARTCharPutNonBlocking(SOC_UART_1_REGS, rxByte);
break;

case UART_INTID_RX_LINE_STAT_ERROR:

rxErrorType = UARTRxErrorGet(SOC_UART_1_REGS);

/* Check if Overrun Error has occured. */
if(rxErrorType & UART_LSR_RX_OE)
{
ConsoleUtilsPrintf("\r\nUART Overrun Error occured."
" Reading and Echoing all data in RX FIFO.\r\n");

/* Read the entire RX FIFO and the data in RX Shift register. */
for(idx = 0; idx < (RX_FIFO_SIZE + 1); idx++)
{
rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
ConsoleUtilsPrintf("%c\n", rxByte);
UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);
}

break;
}

/* Check if Break Condition has occured. */
else if(rxErrorType & UART_LSR_RX_BI)
{
ConsoleUtilsPrintf("\r\nUART Break Condition occured.");
}

/* Check if Framing Error has occured. */
else if(rxErrorType & UART_LSR_RX_FE)
{
ConsoleUtilsPrintf("\r\nUART Framing Error occured.");
}

/* Check if Parity Error has occured. */
else if(rxErrorType & UART_LSR_RX_PE)
{
ConsoleUtilsPrintf("\r\nUART Parity Error occured.");
}

ConsoleUtilsPrintf(" Data at the top of RX FIFO is: ");
rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
ConsoleUtilsPrintf("%c\n", rxByte);
UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);

break;

case UART_INTID_CHAR_TIMEOUT:

ConsoleUtilsPrintf("\r\nUART Character Timeout Interrupt occured."
" Reading and Echoing all data in RX FIFO.\r\n");

/* Read all the data in RX FIFO. */
while(TRUE == UARTCharsAvail(SOC_UART_1_REGS))
{
rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
ConsoleUtilsPrintf("%c\n", rxByte);
UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);
}

break;

default:
break;
}

}

/*
** This function configures the AINTC to receive UART interrupts.
*/

static void UART1AINTCConfigure(void)
{
/* Initializing the ARM Interrupt Controller. */
IntAINTCInit();

/* Registering the Interrupt Service Routine(ISR). */
IntRegister(SYS_INT_UART1INT, UARTIsr);

/* Setting the priority for the system interrupt in AINTC. */
IntPrioritySet(SYS_INT_UART1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

/* Enabling the system interrupt in AINTC. */
IntSystemEnable(SYS_INT_UART1INT);
}

/******************************* End of file *********************************/

Thanks & Regards,

Shubhakara P S

  • 0
    TI__Expert 8885 points

    Hi Shubhakara,

    Is this the legacy starterware release or the starterware included in the Processor SDK release (like starterware under pdk<>/packages/ti/starterware)? Can you please provide details?

    We do not have support for legacy starterware. You may need to install the Processor SDK and check if you can get the UART in the PDK software.

    Thanks

  • 0 in reply to Aravind Batni
    Prodigy 240 points

    Hi Aravind,

    This one is the starterware included in the processors SDK release, I have resolved this issue for UART1 , I am working on UART2 I got stuck at  UartInterruptEnable(); function. for your reference I am pasting my code here pls let me know if anything wrong in my code.

    File :-  C:\ti\AM335X_StarterWare_02_00_01_01\platform\beaglebone/uart.c 

    /**
    * \file uart.c
    *
    * \brief This file contains functions which does the platform specific
    * configurations for UART.
    */

    /*
    * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
    */
    /*
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
    * are met:
    *
    * Redistributions of source code must retain the above copyright
    * notice, this list of conditions and the following disclaimer.
    *
    * Redistributions in binary form must reproduce the above copyright
    * notice, this list of conditions and the following disclaimer in the
    * documentation and/or other materials provided with the
    * distribution.
    *
    * Neither the name of Texas Instruments Incorporated nor the names of
    * its contributors may be used to endorse or promote products derived
    * from this software without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
    * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
    * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
    * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
    * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
    * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
    * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    */


    #include "hw_control_AM335x.h"
    #include "soc_AM335x.h"
    #include "hw_cm_wkup.h"
    #include "hw_cm_per.h"
    #include "beaglebone.h"
    #include "hw_types.h"

    /**
    * \brief This function selects the UART pins for use. The UART pins
    * are multiplexed with pins of other peripherals in the SoC
    *
    * \param instanceNum The instance number of the UART to be used.
    *
    * \return None.
    *
    * \note This pin multiplexing depends on the profile in which the EVM
    * is configured.
    */
    void UARTPinMuxSetup(unsigned int instanceNum)
    {
    if(0 == instanceNum)
    {
    /* UART0 RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(0)) =
    (CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL |
    CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE);

    /* UART0 TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) =
    CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL;
    }
    // Added By shubhakar
    else if(1 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(1)) =
    (CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL |
    CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE);

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(1)) =
    CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL;
    }
    else if(2 == instanceNum)
    {
    /* RXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RXD(2)) =
    (CONTROL_CONF_UART2_RXD_CONF_UART2_RXD_PUTYPESEL |
    CONTROL_CONF_UART2_RXD_CONF_UART2_RXD_RXACTIVE);

    /* TXD */
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_TXD(2)) =
    CONTROL_CONF_UART2_TXD_CONF_UART2_TXD_PUTYPESEL;
    }
    }

    /*
    ** This function enables the system L3 and system L4_WKUP clocks.
    ** This also enables the clocks for UART0 instance.
    */

    void UART0ModuleClkConfig(void)
    {
    /* Configuring L3 Interface Clocks. */

    /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |=
    CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_MODULEMODE));

    /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |=
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE));

    /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |=
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /* Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |=
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |=
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL));

    /* Checking fields for necessary values. */

    /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */
    while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_IDLEST));

    /*
    ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the
    ** desired value.
    */
    while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC <<
    CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to
    ** attain the desired value.
    */
    while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL
    ** register to attain the desired value.
    */
    while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register
    ** to attain the desired value.
    */
    while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));


    /* Configuring registers related to Wake-Up region. */

    /* Writing to MODULEMODE field of CM_WKUP_CONTROL_CLKCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) |=
    CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_WKUP_CONTROL_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
    CM_WKUP_CONTROL_CLKCTRL_MODULEMODE));

    /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) |=
    CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_WKUP_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKTRCTRL));

    /* Writing to CLKTRCTRL field of CM_L3_AON_CLKSTCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) |=
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    /*Waiting for CLKTRCTRL field to reflect the written value. */
    while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL_SW_WKUP !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKTRCTRL));

    /* Writing to MODULEMODE field of CM_WKUP_UART0_CLKCTRL register. */
    HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) |=
    CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE;

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_WKUP_UART0_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
    CM_WKUP_UART0_CLKCTRL_MODULEMODE));

    /* Verifying if the other bits are set to required settings. */

    /*
    ** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CONTROL_CLKCTRL) &
    CM_WKUP_CONTROL_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
    CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));

    /*
    ** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_L4WKUP_CLKCTRL) &
    CM_WKUP_L4WKUP_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
    ** to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
    CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));

    /*
    ** Waiting for CLKACTIVITY_UART0_GFCLK field in CM_WKUP_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_CLKSTCTRL) &
    CM_WKUP_CLKSTCTRL_CLKACTIVITY_UART0_GFCLK));

    /*
    ** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_UART0_CLKCTRL_IDLEST_FUNC <<
    CM_WKUP_UART0_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_WKUP_REGS + CM_WKUP_UART0_CLKCTRL) &
    CM_WKUP_UART0_CLKCTRL_IDLEST));
    }

    /****************************** End of file *********************************/
    void UART1ModuleClkConfig(void)
    {
    #if 1
    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
    CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
    CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
    CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);


    HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) |= CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE;


    while((HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
    CM_PER_UART1_CLKCTRL_MODULEMODE) != CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE);

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK)));


    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
    CM_PER_UART1_CLKCTRL_MODULEMODE));

    /*
    ** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_PER_UART1_CLKCTRL_IDLEST_FUNC <<
    CM_PER_UART1_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART1_CLKCTRL) &
    CM_PER_UART1_CLKCTRL_IDLEST));
    #endif

    #if 0
    HWREG(SOC_PRCM_REGS + CM_PER_UART1_CLKCTRL) |=
    CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_PRCM_REGS + CM_PER_UART1_CLKCTRL) &
    CM_PER_UART1_CLKCTRL_MODULEMODE) != CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE);

    while(!(HWREG(SOC_PRCM_REGS + CM_PER_L4LS_CLKSTCTRL) &
    (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK)));
    #endif

    }
    void UART2ModuleClkConfig(void)
    {

    HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) =
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) =
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKTRCTRL) != CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) =
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) &
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE) !=
    CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) =
    CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) &
    CM_PER_L3_CLKCTRL_MODULEMODE) != CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE);

    HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) =
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL) !=
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) =
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL) !=
    CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP);

    HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) =
    CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE;

    while((HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) &
    CM_PER_L4LS_CLKCTRL_MODULEMODE) != CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE);


    HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) |= CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE;


    while((HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
    CM_PER_UART2_CLKCTRL_MODULEMODE) != CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE);

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) &
    CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) &
    CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) &
    (CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK |
    CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)));

    while(!(HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) &
    (CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK |
    CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK)));


    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
    CM_PER_UART2_CLKCTRL_MODULEMODE));

    /*
    ** Waiting for IDLEST field in CM_WKUP_UART0_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_PER_UART2_CLKCTRL_IDLEST_FUNC <<
    CM_PER_UART2_CLKCTRL_IDLEST_SHIFT) !=
    (HWREG(SOC_CM_PER_REGS + CM_PER_UART2_CLKCTRL) &
    CM_PER_UART2_CLKCTRL_IDLEST));

    }

    File :- dex_Uart2.c (main)

    /*
    * dex_Uart2.c
    *
    * Created on: May 18, 2021
    * Author: Shubhakar
    */


    #include "uart_irda_cir.h"
    #include "soc_AM335x.h"
    #include "interrupt.h"
    #include "beaglebone.h"
    #include "consoleUtils.h"
    #include "hw_types.h"

    /******************************************************************************
    ** INTERNAL MACRO DEFINITIONS
    ******************************************************************************/
    #define BAUD_RATE_115200 (115200)
    #define UART_MODULE_INPUT_CLK (48000000)

    /*
    ** The number of data bytes to be transmitted to Transmit FIFO of UART
    ** per generation of the Transmit Empty interrupt. This can take a maximum
    ** value of TX Trigger Space which is 'TX FIFO size - TX Threshold Level'.
    */
    #define NUM_TX_BYTES_PER_TRANS (56)

    /******************************************************************************
    ** INTERNAL FUNCTION PROTOTYPES
    ******************************************************************************/
    static void UartInterruptEnable(void);
    static void UART2AINTCConfigure(void);
    static void UartFIFOConfigure(void);
    static void UartBaudRateSet(void);
    static void UARTIsr(void);

    /******************************************************************************
    ** GLOBAL VARIABLE DEFINITIONS
    ******************************************************************************/
    unsigned char txArray[] = "StarterWare AM335X UART Interrupt application\r\n";

    /* A flag used to signify the application to transmit data to UART TX FIFO. */
    unsigned int txEmptyFlag = FALSE;

    /*
    ** A variable which holds the number of bytes of the data block transmitted to
    ** UART TX FIFO until the current instant.
    */
    unsigned int currNumTxBytes = 0;

    /******************************************************************************
    ** FUNCTION DEFINITIONS
    ******************************************************************************/

    int main()
    {
    unsigned int numByteChunks = 0;
    unsigned int remainBytes = 0;
    unsigned int bIndex = 0;

    /* Configuring the system clocks for UART2 instance. */
    UART2ModuleClkConfig();

    /* Performing the Pin Multiplexing for UART2 instance. */
    UARTPinMuxSetup(2);

    /* Performing a module reset. */
    UARTModuleReset(SOC_UART_2_REGS);

    /* Performing FIFO configurations. */
    UartFIFOConfigure();

    /* Performing Baud Rate settings. */
    UartBaudRateSet();

    /* Switching to Configuration Mode B. */
    UARTRegConfigModeEnable(SOC_UART_2_REGS, UART_REG_CONFIG_MODE_B);

    /* Programming the Line Characteristics. */
    UARTLineCharacConfig(SOC_UART_2_REGS,
    (UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
    UART_PARITY_NONE);

    /* Disabling write access to Divisor Latches. */
    UARTDivisorLatchDisable(SOC_UART_2_REGS);

    /* Disabling Break Control. */
    UARTBreakCtl(SOC_UART_2_REGS, UART_BREAK_COND_DISABLE);

    /* Switching to UART16x operating mode. */
    UARTOperatingModeSelect(SOC_UART_2_REGS, UART16x_OPER_MODE);

    /* Select the console type based on compile time check */
    ConsoleUtilsSetType(CONSOLE_UART);

    /* Performing Interrupt configurations. */
    UartInterruptEnable();
    numByteChunks = (sizeof(txArray) - 1) / NUM_TX_BYTES_PER_TRANS;
    remainBytes = (sizeof(txArray) - 1) % NUM_TX_BYTES_PER_TRANS;

    #if 0
    UARTFIFOWrite(SOC_UART_2_REGS, "Hello World",0x0B);
    unsigned char recv_array[11] = {0}, tx_array[11] = {"Hello World"};

    int i = 0;
    for (i = 0; i < 11; i++){
    UARTFIFOCharPut(SOC_UART_2_REGS, tx_array[i] );
    recv_array[i] = UARTFIFOCharGet(SOC_UART_2_REGS);
    }
    #endif

    #if 1

    while(1)
    {
    /* This branch is entered if the transmission is not yet complete. */
    if(TRUE == txEmptyFlag)
    {
    if(bIndex < numByteChunks)
    {
    /* Transmitting bytes in chunks of NUM_TX_BYTES_PER_TRANS. */
    currNumTxBytes += UARTFIFOWrite(SOC_UART_2_REGS,
    &txArray[currNumTxBytes],
    NUM_TX_BYTES_PER_TRANS);

    bIndex++;
    }

    else
    {
    /* Transmitting remaining data from the data block. */
    currNumTxBytes += UARTFIFOWrite(SOC_UART_2_REGS,
    &txArray[currNumTxBytes],
    remainBytes);
    }

    txEmptyFlag = FALSE;

    /*
    ** Re-enables the Transmit Interrupt. This interrupt
    ** was disabled in the Transmit section of the UART ISR.
    */
    // UARTIntEnable(SOC_UART_2_REGS, UART_INT_THR);

    }
    }

    #endif
    }

    /*
    ** A wrapper function performing FIFO configurations.
    */

    static void UartFIFOConfigure(void)
    {
    unsigned int fifoConfig = 0;

    /*
    ** - Transmit Trigger Level Granularity is 4
    ** - Receiver Trigger Level Granularity is 1
    ** - Transmit FIFO Space Setting is 56. Hence TX Trigger level
    ** is 8 (64 - 56). The TX FIFO size is 64 bytes.
    ** - The Receiver Trigger Level is 1.
    ** - Clear the Transmit FIFO.
    ** - Clear the Receiver FIFO.
    ** - DMA Mode enabling shall happen through SCR register.
    ** - DMA Mode 0 is enabled. DMA Mode 0 corresponds to No
    ** DMA Mode. Effectively DMA Mode is disabled.
    */
    fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_4,
    UART_TRIG_LVL_GRANULARITY_1,
    UART_FCR_TX_TRIG_LVL_56,
    1,
    1,
    1,
    UART_DMA_EN_PATH_SCR,
    UART_DMA_MODE_0_ENABLE);

    /* Configuring the FIFO settings. */
    UARTFIFOConfig(SOC_UART_2_REGS, fifoConfig);
    }

    /*
    ** A wrapper function performing Baud Rate settings.
    */

    static void UartBaudRateSet(void)
    {
    unsigned int divisorValue = 0;

    /* Computing the Divisor Value. */
    divisorValue = UARTDivisorValCompute(UART_MODULE_INPUT_CLK,
    BAUD_RATE_115200,
    UART16x_OPER_MODE,
    UART_MIR_OVERSAMPLING_RATE_42);

    /* Programming the Divisor Latches. */
    UARTDivisorLatchWrite(SOC_UART_2_REGS, divisorValue);
    }

    /*
    ** A wrapper function performing Interrupt configurations.
    */

    static void UartInterruptEnable(void)
    {
    /* Enabling IRQ in CPSR of ARM processor. */
    IntMasterIRQEnable();

    /* Configuring AINTC to receive UART0 interrupts. */
    UART2AINTCConfigure();

    /* Enabling the specified UART interrupts. */
    UARTIntEnable(SOC_UART_2_REGS, (UART_INT_LINE_STAT | UART_INT_THR |
    UART_INT_RHR_CTI));
    // UARTIsr();
    }

    /*
    ** Interrupt Service Routine for UART.
    */

    static void UARTIsr(void)
    {
    unsigned int rxErrorType = 0;
    unsigned char rxByte = 0;
    unsigned int intId = 0;
    unsigned int idx = 0;

    /* Checking ths source of UART interrupt. */
    intId = UARTIntIdentityGet(SOC_UART_2_REGS);

    switch(intId)
    {
    case UART_INTID_TX_THRES_REACH:

    /*
    ** Checking if the entire transmisssion is complete. If this
    ** condition fails, then the entire transmission has been completed.
    */
    if(currNumTxBytes < (sizeof(txArray) - 1))
    {
    txEmptyFlag = TRUE;
    }

    /*
    ** Disable the THR interrupt. This has to be done even if the
    ** transmission is not complete so as to prevent the Transmit
    ** empty interrupt to be continuously generated.
    */
    UARTIntDisable(SOC_UART_2_REGS, UART_INT_THR);

    break;

    case UART_INTID_RX_THRES_REACH:
    rxByte = UARTCharGetNonBlocking(SOC_UART_2_REGS);
    UARTCharPutNonBlocking(SOC_UART_2_REGS, rxByte);
    break;

    case UART_INTID_RX_LINE_STAT_ERROR:

    rxErrorType = UARTRxErrorGet(SOC_UART_2_REGS);

    /* Check if Overrun Error has occured. */
    if(rxErrorType & UART_LSR_RX_OE)
    {
    ConsoleUtilsPrintf("\r\nUART Overrun Error occured."
    " Reading and Echoing all data in RX FIFO.\r\n");

    /* Read the entire RX FIFO and the data in RX Shift register. */
    for(idx = 0; idx < (RX_FIFO_SIZE + 1); idx++)
    {
    rxByte = UARTFIFOCharGet(SOC_UART_2_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_2_REGS, rxByte);
    }

    break;
    }

    /* Check if Break Condition has occured. */
    else if(rxErrorType & UART_LSR_RX_BI)
    {
    ConsoleUtilsPrintf("\r\nUART Break Condition occured.");
    }

    /* Check if Framing Error has occured. */
    else if(rxErrorType & UART_LSR_RX_FE)
    {
    ConsoleUtilsPrintf("\r\nUART Framing Error occured.");
    }

    /* Check if Parity Error has occured. */
    else if(rxErrorType & UART_LSR_RX_PE)
    {
    ConsoleUtilsPrintf("\r\nUART Parity Error occured.");
    }

    ConsoleUtilsPrintf(" Data at the top of RX FIFO is: ");
    rxByte = UARTFIFOCharGet(SOC_UART_2_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_2_REGS, rxByte);

    break;

    case UART_INTID_CHAR_TIMEOUT:

    ConsoleUtilsPrintf("\r\nUART Character Timeout Interrupt occured."
    " Reading and Echoing all data in RX FIFO.\r\n");

    /* Read all the data in RX FIFO. */
    while(TRUE == UARTCharsAvail(SOC_UART_2_REGS))
    {
    rxByte = UARTFIFOCharGet(SOC_UART_2_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_2_REGS, rxByte);
    }

    break;

    default:
    break;
    }

    }

    /*
    ** This function configures the AINTC to receive UART interrupts.
    */

    static void UART2AINTCConfigure(void)
    {
    /* Initializing the ARM Interrupt Controller. */
    IntAINTCInit();

    /* Registering the Interrupt Service Routine(ISR). */
    IntRegister(SYS_INT_UART2INT, UARTIsr);

    /* Setting the priority for the system interrupt in AINTC. */
    IntPrioritySet(SYS_INT_UART2INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the system interrupt in AINTC. */
    IntSystemEnable(SYS_INT_UART2INT);
    }

    /******************************* End of file *********************************/

    File :- dex_Uart1.c (main)

    /*
    * dex_Uart1.c
    *
    * Created on: May 18, 2021
    * Author: Shubhakar
    */


    #include "uart_irda_cir.h"
    #include "soc_AM335x.h"
    #include "interrupt.h"
    #include "beaglebone.h"
    #include "consoleUtils.h"
    #include "hw_types.h"

    /******************************************************************************
    ** INTERNAL MACRO DEFINITIONS
    ******************************************************************************/
    #define BAUD_RATE_115200 (115200)
    #define UART_MODULE_INPUT_CLK (48000000)

    /*
    ** The number of data bytes to be transmitted to Transmit FIFO of UART
    ** per generation of the Transmit Empty interrupt. This can take a maximum
    ** value of TX Trigger Space which is 'TX FIFO size - TX Threshold Level'.
    */
    #define NUM_TX_BYTES_PER_TRANS (56)

    /******************************************************************************
    ** INTERNAL FUNCTION PROTOTYPES
    ******************************************************************************/
    static void UartInterruptEnable(void);
    static void UART1AINTCConfigure(void);
    static void UartFIFOConfigure(void);
    static void UartBaudRateSet(void);
    static void UARTIsr(void);

    /******************************************************************************
    ** GLOBAL VARIABLE DEFINITIONS
    ******************************************************************************/
    unsigned char txArray[] = "StarterWare AM335X UART Interrupt application\r\n";

    /* A flag used to signify the application to transmit data to UART TX FIFO. */
    unsigned int txEmptyFlag = FALSE;

    /*
    ** A variable which holds the number of bytes of the data block transmitted to
    ** UART TX FIFO until the current instant.
    */
    unsigned int currNumTxBytes = 0;

    /******************************************************************************
    ** FUNCTION DEFINITIONS
    ******************************************************************************/

    int main()
    {
    unsigned int numByteChunks = 0;
    unsigned int remainBytes = 0;
    unsigned int bIndex = 0;

    /* Configuring the system clocks for UART0 instance. */
    UART1ModuleClkConfig();

    /* Performing the Pin Multiplexing for UART0 instance. */
    UARTPinMuxSetup(1);

    /* Performing a module reset. */
    UARTModuleReset(SOC_UART_1_REGS);

    /* Performing FIFO configurations. */
    UartFIFOConfigure();

    /* Performing Baud Rate settings. */
    UartBaudRateSet();

    /* Switching to Configuration Mode B. */
    UARTRegConfigModeEnable(SOC_UART_1_REGS, UART_REG_CONFIG_MODE_B);

    /* Programming the Line Characteristics. */
    UARTLineCharacConfig(SOC_UART_1_REGS,
    (UART_FRAME_WORD_LENGTH_8 | UART_FRAME_NUM_STB_1),
    UART_PARITY_NONE);

    /* Disabling write access to Divisor Latches. */
    UARTDivisorLatchDisable(SOC_UART_1_REGS);

    /* Disabling Break Control. */
    UARTBreakCtl(SOC_UART_1_REGS, UART_BREAK_COND_DISABLE);

    /* Switching to UART16x operating mode. */
    UARTOperatingModeSelect(SOC_UART_1_REGS, UART16x_OPER_MODE);

    /* Select the console type based on compile time check */
    ConsoleUtilsSetType(CONSOLE_UART);

    /* Performing Interrupt configurations. */
    UartInterruptEnable();
    numByteChunks = (sizeof(txArray) - 1) / NUM_TX_BYTES_PER_TRANS;
    remainBytes = (sizeof(txArray) - 1) % NUM_TX_BYTES_PER_TRANS;


    #if 0
    UARTFIFOWrite(SOC_UART_1_REGS, "Hello World",0x0B);
    unsigned char recv_array[11] = {0}, tx_array[11] = {"Hello World"};

    int i = 0;
    for (i = 0; i < 11; i++){
    UARTFIFOCharPut(SOC_UART_1_REGS, tx_array[i] );
    recv_array[i] = UARTFIFOCharGet(SOC_UART_1_REGS);
    }
    #endif

    #if 1

    while(1)
    {
    /* This branch is entered if the transmission is not yet complete. */
    if(TRUE == txEmptyFlag)
    {
    if(bIndex < numByteChunks)
    {
    /* Transmitting bytes in chunks of NUM_TX_BYTES_PER_TRANS. */
    currNumTxBytes += UARTFIFOWrite(SOC_UART_1_REGS,
    &txArray[currNumTxBytes],
    NUM_TX_BYTES_PER_TRANS);

    bIndex++;
    }

    else
    {
    /* Transmitting remaining data from the data block. */
    currNumTxBytes += UARTFIFOWrite(SOC_UART_1_REGS,
    &txArray[currNumTxBytes],
    remainBytes);
    }

    txEmptyFlag = FALSE;

    /*
    ** Re-enables the Transmit Interrupt. This interrupt
    ** was disabled in the Transmit section of the UART ISR.
    */
    UARTIntEnable(SOC_UART_1_REGS, UART_INT_THR);

    }
    }

    #endif
    }

    /*
    ** A wrapper function performing FIFO configurations.
    */

    static void UartFIFOConfigure(void)
    {
    unsigned int fifoConfig = 0;

    /*
    ** - Transmit Trigger Level Granularity is 4
    ** - Receiver Trigger Level Granularity is 1
    ** - Transmit FIFO Space Setting is 56. Hence TX Trigger level
    ** is 8 (64 - 56). The TX FIFO size is 64 bytes.
    ** - The Receiver Trigger Level is 1.
    ** - Clear the Transmit FIFO.
    ** - Clear the Receiver FIFO.
    ** - DMA Mode enabling shall happen through SCR register.
    ** - DMA Mode 0 is enabled. DMA Mode 0 corresponds to No
    ** DMA Mode. Effectively DMA Mode is disabled.
    */
    fifoConfig = UART_FIFO_CONFIG(UART_TRIG_LVL_GRANULARITY_4,
    UART_TRIG_LVL_GRANULARITY_1,
    UART_FCR_TX_TRIG_LVL_56,
    1,
    1,
    1,
    UART_DMA_EN_PATH_SCR,
    UART_DMA_MODE_0_ENABLE);

    /* Configuring the FIFO settings. */
    UARTFIFOConfig(SOC_UART_1_REGS, fifoConfig);
    }

    /*
    ** A wrapper function performing Baud Rate settings.
    */

    static void UartBaudRateSet(void)
    {
    unsigned int divisorValue = 0;

    /* Computing the Divisor Value. */
    divisorValue = UARTDivisorValCompute(UART_MODULE_INPUT_CLK,
    BAUD_RATE_115200,
    UART16x_OPER_MODE,
    UART_MIR_OVERSAMPLING_RATE_42);

    /* Programming the Divisor Latches. */
    UARTDivisorLatchWrite(SOC_UART_1_REGS, divisorValue);
    }

    /*
    ** A wrapper function performing Interrupt configurations.
    */

    static void UartInterruptEnable(void)
    {
    /* Enabling IRQ in CPSR of ARM processor. */
    IntMasterIRQEnable();

    /* Configuring AINTC to receive UART0 interrupts. */
    UART1AINTCConfigure();

    /* Enabling the specified UART interrupts. */
    UARTIntEnable(SOC_UART_1_REGS, (UART_INT_LINE_STAT | UART_INT_THR |
    UART_INT_RHR_CTI));
    // UARTIsr();
    }

    /*
    ** Interrupt Service Routine for UART.
    */

    static void UARTIsr(void)
    {
    unsigned int rxErrorType = 0;
    unsigned char rxByte = 0;
    unsigned int intId = 0;
    unsigned int idx = 0;

    /* Checking ths source of UART interrupt. */
    intId = UARTIntIdentityGet(SOC_UART_1_REGS);

    switch(intId)
    {
    case UART_INTID_TX_THRES_REACH:

    /*
    ** Checking if the entire transmisssion is complete. If this
    ** condition fails, then the entire transmission has been completed.
    */
    if(currNumTxBytes < (sizeof(txArray) - 1))
    {
    txEmptyFlag = TRUE;
    }

    /*
    ** Disable the THR interrupt. This has to be done even if the
    ** transmission is not complete so as to prevent the Transmit
    ** empty interrupt to be continuously generated.
    */
    UARTIntDisable(SOC_UART_1_REGS, UART_INT_THR);

    break;

    case UART_INTID_RX_THRES_REACH:
    rxByte = UARTCharGetNonBlocking(SOC_UART_1_REGS);
    UARTCharPutNonBlocking(SOC_UART_1_REGS, rxByte);
    break;

    case UART_INTID_RX_LINE_STAT_ERROR:

    rxErrorType = UARTRxErrorGet(SOC_UART_1_REGS);

    /* Check if Overrun Error has occured. */
    if(rxErrorType & UART_LSR_RX_OE)
    {
    ConsoleUtilsPrintf("\r\nUART Overrun Error occured."
    " Reading and Echoing all data in RX FIFO.\r\n");

    /* Read the entire RX FIFO and the data in RX Shift register. */
    for(idx = 0; idx < (RX_FIFO_SIZE + 1); idx++)
    {
    rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);
    }

    break;
    }

    /* Check if Break Condition has occured. */
    else if(rxErrorType & UART_LSR_RX_BI)
    {
    ConsoleUtilsPrintf("\r\nUART Break Condition occured.");
    }

    /* Check if Framing Error has occured. */
    else if(rxErrorType & UART_LSR_RX_FE)
    {
    ConsoleUtilsPrintf("\r\nUART Framing Error occured.");
    }

    /* Check if Parity Error has occured. */
    else if(rxErrorType & UART_LSR_RX_PE)
    {
    ConsoleUtilsPrintf("\r\nUART Parity Error occured.");
    }

    ConsoleUtilsPrintf(" Data at the top of RX FIFO is: ");
    rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);

    break;

    case UART_INTID_CHAR_TIMEOUT:

    ConsoleUtilsPrintf("\r\nUART Character Timeout Interrupt occured."
    " Reading and Echoing all data in RX FIFO.\r\n");

    /* Read all the data in RX FIFO. */
    while(TRUE == UARTCharsAvail(SOC_UART_1_REGS))
    {
    rxByte = UARTFIFOCharGet(SOC_UART_1_REGS);
    ConsoleUtilsPrintf("%c\n", rxByte);
    UARTFIFOCharPut(SOC_UART_1_REGS, rxByte);
    }

    break;

    default:
    break;
    }

    }

    /*
    ** This function configures the AINTC to receive UART interrupts.
    */

    static void UART1AINTCConfigure(void)
    {
    /* Initializing the ARM Interrupt Controller. */
    IntAINTCInit();

    /* Registering the Interrupt Service Routine(ISR). */
    IntRegister(SYS_INT_UART1INT, UARTIsr);

    /* Setting the priority for the system interrupt in AINTC. */
    IntPrioritySet(SYS_INT_UART1INT, 0, AINTC_HOSTINT_ROUTE_IRQ);

    /* Enabling the system interrupt in AINTC. */
    IntSystemEnable(SYS_INT_UART1INT);
    }

    /******************************* End of file *********************************/

    Thanks & Regards,

    Shubhakara P S

  • 0 in reply to Shubhakara P S
    TI__Intellectual 2360 points

    Hi Shubhakara,

    My name is Andrew, and I would be more than happy to assist you with this question.  Thank you for the information that you have provided. I am consulting with my colleagues on this now and we will try to have an answer/followup for you within the next 24-48 hours.

    Best regards,

    Andrew

     

  • 0 in reply to Andrew Shutzberg
    Prodigy 240 points

    Alright and Thanks Andrew.

    Regards,

    Shubhakara P S

  • 0 in reply to Shubhakara P S
    TI__Intellectual 2360 points

    Hello Shubhakara,

    My sincerest apologies, would you be able to upload your files instead of posting the text?  We are having some difficulty recreating your problem with the snippet you provided.

    In the meantime I will continue to investigate this.

    Best regards,

    Andrew

  • 0 in reply to Andrew Shutzberg
    TI__Intellectual 2360 points

    Hello Shubhakara,

    Just checking in, are you still having this issue?  If so, are you able to upload the relevant file(s)?

    Best regards,

    Andrew