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I'm sorry, could you please provide more details on what you are requesting. I do not understand 'custom layer creation'? Are you referring to a sample PCB stack-up?
There is recently a source release to you, please refer the document in that package at blow path
ti_dl/docs/user_guide_nda_html/md_tidl_custom_layer.html
or alternatively request access via below link
7. Data Sheet — Processor SDK RTOS J721E (ti.com)
Thanks,
With Regards,
Pramod