TMDX654IDKEVM: Enabling DDR4 ECC

Hi,

To confirm, you are using the TI EVM and are observing the write leveling adjustment error? Can you attach the full DTSI file you are using?

Thanks,

Kevin

Hi Kevin,

I am using two TMDX654IDKEVM boards and the write leveling adjustment error appears on both.

Please, find attached the k3-am654-base-board-ddr4-1600MTs.dtsi file.

Thank you for your fast reply.

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
* www.ti.com/.../spracj0
* Configuration Parameters
* Memory Type: DDR4
* Data Rate: 1600 MT/s
* ECC Enabled: Yes
* Data Width: 32 bits
*/
#define DDR_PLL_FREQUENCY 400000000
#define DDRSS_V2H_CTL_REG 0x800073FF
#define DDRCTL_MSTR 0x41040010
#define DDRCTL_RFSHCTL0 0x00210070
#define DDRCTL_ECCCFG0 0x00000014
#define DDRCTL_RFSHTMG 0x0061008C
#define DDRCTL_CRCPARCTL0 0x00008000
#define DDRCTL_CRCPARCTL1 0x1A000000
#define DDRCTL_CRCPARCTL2 0x0048051E
#define DDRCTL_INIT0 0x400100C4
#define DDRCTL_INIT1 0x004F0000
#define DDRCTL_INIT3 0x02140501
#define DDRCTL_INIT4 0x00000020
#define DDRCTL_INIT5 0x00100000
#define DDRCTL_INIT6 0x00000480
#define DDRCTL_INIT7 0x00000497
#define DDRCTL_DRAMTMG0 0x0C0A1B0D
#define DDRCTL_DRAMTMG1 0x00030313
#define DDRCTL_DRAMTMG2 0x0506050A
#define DDRCTL_DRAMTMG3 0x0000400C
#define DDRCTL_DRAMTMG4 0x06020206
#define DDRCTL_DRAMTMG5 0x04040302
#define DDRCTL_DRAMTMG6 0x00000004
#define DDRCTL_DRAMTMG7 0x00000404
#define DDRCTL_DRAMTMG8 0x03030C05
#define DDRCTL_DRAMTMG9 0x00020208
#define DDRCTL_DRAMTMG10 0x001C180A
#define DDRCTL_DRAMTMG11 0x1106010E
#define DDRCTL_DRAMTMG12 0x00020008
#define DDRCTL_DRAMTMG13 0x0B100002
#define DDRCTL_DRAMTMG14 0x00000000
#define DDRCTL_DRAMTMG15 0x0000003F
#define DDRCTL_DRAMTMG17 0x00500028
#define DDRCTL_ZQCTL0 0x21000040
#define DDRCTL_ZQCTL1 0x0202FAF0
#define DDRCTL_DFITMG0 0x04888206
#define DDRCTL_DFITMG1 0x000A0606
#define DDRCTL_DFITMG2 0x00000604
#define DDRCTL_DFIMISC 0x00000001
#define DDRCTL_ADDRMAP0 0x0000001F
#define DDRCTL_ADDRMAP1 0x003F0808
#define DDRCTL_ADDRMAP2 0x00000000
#define DDRCTL_ADDRMAP3 0x00000000
#define DDRCTL_ADDRMAP4 0x00001F1F
#define DDRCTL_ADDRMAP5 0x08080808
#define DDRCTL_ADDRMAP6 0x08080808
#define DDRCTL_ADDRMAP7 0x00000F0F
#define DDRCTL_ADDRMAP8 0x00000A0A
#define DDRCTL_ADDRMAP9 0x00000000
#define DDRCTL_ADDRMAP10 0x00000000
#define DDRCTL_ADDRMAP11 0x001F1F00
#define DDRCTL_DQMAP0 0x00000000
#define DDRCTL_DQMAP1 0x00000000
#define DDRCTL_DQMAP4 0x00000000
#define DDRCTL_DQMAP5 0x00000000
#define DDRCTL_PWRCTL 0x00000000
#define DDRCTL_RANKCTL 0x00000000
#define DDRCTL_ODTCFG 0x0600060C
#define DDRCTL_ODTMAP 0x00000001
#define DDRPHY_PGCR0 0x07001E00
#define DDRPHY_PGCR1 0x020046C0
#define DDRPHY_PGCR2 0x00F0BFE0
#define DDRPHY_PGCR3 0x55AA0080
#define DDRPHY_PGCR6 0x00013001
#define DDRPHY_PTR2 0x00083DEF
#define DDRPHY_PTR3 0x00061A80
#define DDRPHY_PTR4 0x00000120
#define DDRPHY_PTR5 0x00027100
#define DDRPHY_PTR6 0x04000320
#define DDRPHY_PLLCR0 0x021c4000
#define DDRPHY_DXCCR 0x00000038
#define DDRPHY_DSGCR 0x02A0C129
#define DDRPHY_DCR 0x0000040C
#define DDRPHY_DTPR0 0x041A0B06
#define DDRPHY_DTPR1 0x28140000
#define DDRPHY_DTPR2 0x0034E300
#define DDRPHY_DTPR3 0x02800800
#define DDRPHY_DTPR4 0x31180805
#define DDRPHY_DTPR5 0x00250B06
#define DDRPHY_DTPR6 0x00000505
#define DDRPHY_ZQCR 0x008A2A58
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x00007799
#define DDRPHY_MR0 0x00000214
#define DDRPHY_MR1 0x00000501
#define DDRPHY_MR2 0x00000000
#define DDRPHY_MR3 0x00000020
#define DDRPHY_MR4 0x00000000
#define DDRPHY_MR5 0x00000480
#define DDRPHY_MR6 0x00000497
#define DDRPHY_MR11 0x00000000
#define DDRPHY_MR12 0x00000000
#define DDRPHY_MR13 0x00000000
#define DDRPHY_MR14 0x00000000
#define DDRPHY_MR22 0x00000000
#define DDRPHY_VTCR0 0xF3C32017
#define DDRPHY_DX8SL0PLLCR0 0x021c4000
#define DDRPHY_DX8SL1PLLCR0 0x021c4000
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
#define DDRPHY_DTCR0 0x8000B1C7
#define DDRPHY_DTCR1 0x00010236
#define DDRPHY_ACIOCR0 0xF0070000
#define DDRPHY_ACIOCR3 0x00000001
#define DDRPHY_ACIOCR5 0x04800000
#define DDRPHY_IOVCR0 0x0F0C0C0C
#define DDRPHY_DX0GCR0 0x00000000
#define DDRPHY_DX0GCR1 0x00000000
#define DDRPHY_DX0GCR2 0x00000000
#define DDRPHY_DX0GCR3 0x00000000
#define DDRPHY_DX1GCR0 0x00000000
#define DDRPHY_DX1GCR1 0x00000000
#define DDRPHY_DX1GCR2 0x00000000
#define DDRPHY_DX1GCR3 0x00000000
#define DDRPHY_DX2GCR0 0x40700204
#define DDRPHY_DX2GCR1 0x00007FFF
#define DDRPHY_DX2GCR2 0x00000000
#define DDRPHY_DX2GCR3 0xFFC0010B
#define DDRPHY_DX3GCR0 0x40700204
#define DDRPHY_DX3GCR1 0x00007FFF
#define DDRPHY_DX3GCR2 0x00000000
#define DDRPHY_DX3GCR3 0xFFC0010B
#define DDRPHY_DX4GCR0 0x40700204
#define DDRPHY_DX4GCR1 0x00007F7F
#define DDRPHY_DX4GCR2 0x00000000
#define DDRPHY_DX4GCR3 0xFFC0010B
#define DDRPHY_DX0GCR4 0x0E00B03C
#define DDRPHY_DX1GCR4 0x0E00B03C
#define DDRPHY_DX2GCR4 0x0E00B03C
#define DDRPHY_DX3GCR4 0x0E00B03C
#define DDRPHY_DX4GCR4 0x0E00B03C
#define DDRPHY_PGCR5 0x01010004
#define DDRPHY_DX0GCR5 0x00000049
#define DDRPHY_DX1GCR5 0x00000049
#define DDRPHY_DX2GCR5 0x00000049
#define DDRPHY_DX3GCR5 0x00000049
#define DDRPHY_DX4GCR5 0x00000049
#define DDRPHY_DX0GTR0 0x00020002
#define DDRPHY_DX1GTR0 0x00020002
#define DDRPHY_DX2GTR0 0x00020002
#define DDRPHY_DX3GTR0 0x00020002
#define DDRPHY_DX4GTR0 0x00020002
#define DDRPHY_ODTCR 0x00010000
#define DDRPHY_DX8SL0IOCR 0x74800000
#define DDRPHY_DX8SL1IOCR 0x74800000
#define DDRPHY_DX8SL2IOCR 0x74800000
#define DDRPHY_DX8SL0DXCTL2 0x00141830
#define DDRPHY_DX8SL1DXCTL2 0x00141830
#define DDRPHY_DX8SL2DXCTL2 0x00141830
#define DDRPHY_DX8SL0DQSCTL 0x01264300
#define DDRPHY_DX8SL1DQSCTL 0x01264300
#define DDRPHY_DX8SL2DQSCTL 0x01264300

Hi Kevin,

Any news on this topic?

Thank you.

Hi Antonio,

I have not heard back from the creator of the AM65 DDR tool yet. I have sent a follow-up email.

Regards,
Kevin

Hi Antonio,

When ECC is disabled and you are able to get past the DDR initialization, does the boot log report the silicon revision? (ex: "SOC: AM65 SR1.0"?)

Thanks,
Kevin

Hi Kevin,

In both boards the silicon revision is SR2.0:

SoC:   AM65X SR2.0

Thanks.

Hi Antonio,

Thanks, would you be able to try with the GEL and see if the same issue occurs?

A colleague of mine provided the steps below:

Using the default GELs that ship with CCS

C:\ti\ccs1030\ccs\ccs_base\emulation\boards\am65x\gel\M4_DDR39SS\M4_DDR_Config.gel

1. First prove no write leveling occurs with ECC disabled (default)
   1. Confirm R5 GEL “M4_DDR_Config.gel has the below line to disable ECC
      Write_MMR(DDRSS_DDRCTL_ECCCFG0,0x00000000); /* ECC Configuration Register*/
      Initialize DDR with Scripts -> DDR_Initialization -> DDR_Initialization
   2. Check output of training for write leveling errors
   3. Confirm 0x80000000 (DDR space) has no issues writing / reading
2. Next power cycle the EVM, and modify/reload the M4_DDR_Config.gel to enable ECC (with dis_scrub set) and repeat
   1. Confirm R5 GEL “M4_DDR_Config.gel has the below line
      Write_MMR(DDRSS_DDRCTL_ECCCFG0,0x00000014); /* ECC Configuration Register*/ //enabled ECC, disabled scrub (changed 0 to 0x14)
   2. Initialize DDR with Hotmenu DDR_Initialization -> DDR_Initialization
   3. Check output of training for write leveling errors
   4. Study ECC regs for errors before/after init with Scripts->DDR_Testing->ECC_RegDump_Decode
3. Repeat with ECC enabled, but before performing any reads with CCS mem window – execute a program that “primes” the DDR by writing to DDR with DMA – this also writes to ECC, putting valid codes for the data written to DDR.

1. 1. After initialization and priming, ECC regs should report no errors (correctable or uncorrectable)
   2. Writes and reads to DDR (within the region that has been primed) should not generate any ECC errors

Hi Kevin,

I don't understand the purpose of the CCS test that you have proposed.

Do you mean that there's can be something wrong in the procedure followed by the am654_ddrss_init() function to
initialize the ddr4 controller (u-boot file /drivers/ram/k3-am654-ddrss.c) or in the registers value generated by
the AM65x_DRA80xM_EMIF_Tool_2.02 tool?

Hi Kevin,

If the file M4_DDR_Config.gel is used to initialize the DDR controller, with ECC enabled, the "Write Leveling Adjustment" error does not appear, unfortunately, the ECC_RegDump_Decode script reports some errors.

Once the DDR controller is initialized, with ECC enabled, the DDR is primed. The ECC_RegDump_Decode script does not report any error. Then, the first DDR4 memory positions are read. The next ECC errors are displayed:

MCU_PULSAR_Cortex_R5_0: GEL Output: DDR ECC RegDump & Decode...

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCFG0 = 0x00000014

MCU_PULSAR_Cortex_R5_0: GEL Output:  - uncorrected_err_threshold =  0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - eccap_en =  0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - inline_ecc_en = 0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - dis_scrub = 1

MCU_PULSAR_Cortex_R5_0: GEL Output:  - test_mode = 0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_mode =  4 (4 = ECC enabled - SEC/DED over 1 beat)

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCFG1 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - poison_chip_en =  0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - data_poison_bit = 0 (0 -> 2-bit (uncorrectable), 1 -> 1-bit (correctable)

MCU_PULSAR_Cortex_R5_0: GEL Output:  - data_poison_en =  0

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCSTAT = 0x00000F3F

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorrected_err =   0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corrected_err =     15

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corrected_bit_num = 63

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCLR = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCERRCNT = 0x00000048

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_err_cnt = 0

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_err_cnt =   72

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCADDR0 (Corrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_rank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_row =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCADDR1 (Corrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_cid =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_bg =   0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_bank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_corr_col =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCSYN0 (Corrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCCSYN2 (Corrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCBITMASK0 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCBITMASK2 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCUADDR0 (Uncorrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_rank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_row =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCUADDR1 (Uncorrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_cid =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_bg =   0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_bank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_uncorr_col =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCUSYN0 (Uncorrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCUSYN2 (Uncorrected) = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCPOISONADDR0 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_rank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_cid =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_col =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCPOISONADDR1 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_bg =   0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_bank = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output:  - ecc_poison_row =  0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ADVECCINDEX = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCPOISONPAT0 = 0x00000000

MCU_PULSAR_Cortex_R5_0: GEL Output: DDRSS_DDRCTL_ECCPOISONPAT2 = 0x00000000

Hi Antonio,

Is this issue still open or has it been resolved?

If observing ECC errors, have you confirmed that

• The ECC memory region was primed (written) before any read request was made?
• The CCS memory browser window is closed and no other cores are trying to access DDR? 

Thanks,
Kevin