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USB0 PHY Clock problem

Zoltan Horvath
Prodigy 70 points
Other Parts Discussed in Thread: OMAPL138

Hi,

I have problem with initializing USB clock on OMAPL138 chip on ZOOM Logic board. My project is developed using eCos running on ARM core.

I already have a USB project for OMAPL137 (running on DSP core with DSP BIOS) on Spectrum Digital board developed with CCS4. I tried to adapt this project to ZOOM board.

I am using AUXCLK for USB0 clock source. CFGCHIP2 is configured, as described in OMAPLxx USB Controller User's Guide example. The problem is, that the USB0 PHY clock fails, or at least USB0PHYCLKGD bit is not set. USB PHY is enabled (USB0PHYPWDN = 0).

Obviousely I missed something to set correctly, but I don't have any more idea.

Do you have some suggestion what the problem could be?

Thanks

Zoltan

  • 0
    TI__Genius 9460 points

    Zoltan,

    Whats the value of CFGCHIP2 register? Are you sure if AUXCLK is configured correctly?

    Regards,

    Ajay

  • 0 in reply to Ajay
    Prodigy 70 points

    Hello Ajay,

    Thanks for your quick reply.

    CFGCHIP2 is set to 0x00004972.

    BUt here is my USB initialization code:

      /* UNLock SYSCFG Module Registers */
      UNLOCK_CONFIG_REGISTERS

      // Reset the USB controller.
      USB0_CTRLR |= 0x00000001;
      //Wait until controller is finished with Reset. When done, it will clear the RESET bit field.
      while ((USB0_CTRLR & 0x1) == 1);
      // Hold PHY in reset
      CFGCHIP2 |= 0x00008000;
      // Drive Reset for few clock cycles
      for (i=0; i < 500; i++);
      // Release PHY from reset
      CFGCHIP2 &= 0xFFFF7FFF;
      CFGCHIP2 = 0x00004972;

      // Wait until PHY clock is good
      while ((CFGCHIP2 & 0x00020000) == 0);         <---------- Here waits for clock because USB0PHYCLKGD will never be set!!!.

      if(usbd_at_high_speed())
        // Enable high-speed
        USB0_POWER |= USB0_POWER_HSEN;
      else
        // Disable high-speed
        USB0_POWER &= ~USB0_POWER_HSEN;   

      // Enable Interrupts
    ...

     

    Best regards

    Zoltan

  • 0 in reply to Zoltan Horvath
    TI__Genius 9460 points

    Zoltan

    Can you try without doing pHY in reset, avoid below codes.

      // Hold PHY in reset
      CFGCHIP2 |= 0x00008000;
      // Drive Reset for few clock cycles
      for (i=0; i < 500; i++);
      // Release PHY from reset
      CFGCHIP2 &= 0xFFFF7FFF;


    Have you made sure that the board works fine by using BIOS USB code?

    Regards,

    ajay

     


  • 0 in reply to Ajay
    TI__Prodigy 20 points

    Zoltan,

    I think you need to reset the phy, but you can avoid the rest of  the code and try.

    regards

    Biju 

  • 0 in reply to Ajay
    Prodigy 70 points

    Hello Ajay,

     

    First thank you for your help. I found what the problem was. The USB0 was not powered on correctly in PSC.

    In my first project on OMAPL137 DSP BIOS was included, and it initialized PSC. This was not done here.
    Now, PLL is locked. I can keep move forward with development.

    Thank you again.

    Best regards

    Zoltan

  • 0 in reply to Biju Chakkachattil
    Prodigy 70 points

    Hello Biju,

     

    Thank for your reply.  In the meantime I found what was worng.

    The PSC was not configured correctly for USB0. Also see my answer for Ajay.

    Best regards

    Zoltan