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AM3358: ADC Frequency Cutoff

Brandon08
Mastermind 24315 points
Part Number: AM3358

Team,

I have a customer who is using all channels of the on-board ADC. One of these channels is measuring a 1KHz Signal, rest are measuring temperature from NTC or PT1000. They are asking: "What would be the frequency cutoff for the adc?"

Would this information be deduced from table 5-16 of the datasheet (SPRS717L)?

Thanks,

Brandon

  • 0
    TI__Guru 63125 points

    I do not understand you question about cutoff frequency. The ADC does not provide any filtering. However, your specific ADC configuration determines the sample rate of each input. I will try to explain below. 

    It is important that you understand the ADC is only able to perform one measurement at a time, so it may be better to think of it as a single channel ADC with an 8 to 1 analog multiplexer which is can be used to select one of eight inputs.

    The user is able to program a sequence of measurements via steps, where each step is able to have a unique configuration. The steps are executed in sequential order based on which ones you enable or disable. Each step takes a minimum of two ADC clock cycles to acquire the signal, which can be configured via SampleDelay, and a fixed number of 13 ADC clock cycles to perform the conversion. Additional ADC clock cycles can be inserted before the steps begins acquisition and conversion by incrementing the value of OpenDelay. The ADC clock should be configured to operate between 1 and 3 MHz and your configuration of steps will determine the sample rate of each input. For example, the sample rate of a single input being sampled by configuring a single step with min OpenDelay and min Sample Delay operating in continuous mode with a 3MHz ADC clock would be 200 kHz. If you were to add another step, which is required to sample another input, and it also has a min OpenDelay and SampleDelay, the sample rate of each input would be reduced to 100 kHz.

    So the sample rate of any input is completely dependent on how you configure steps, which are used to create a sequence of measurements.

    Regards,
    Paul

  • 0
    Prodigy 40 points

    Does the bottom explanation makes sense?

    ADC Channels Max Clock frequency is set to 3MHz which provides 200ksps
    If we divide the samples by 8 because we are using all 8 channels of ADC (Processor), we are left with 25ksps
    This means that we can capture 1 sample every 40us
    So, we can only capture 25 samples during 1000us (1ms==1KHz Pilot Signal)

  • 0 in reply to peaves
    Prodigy 40 points

    Does the bottom explanation makes sense?

    ADC Channels Max Clock frequency is set to 3MHz which provides 200ksps
    If we divide the samples by 8 because we are using all 8 channels of ADC (Processor), we are left with 25ksps
    This means that we can capture 1 sample every 40us
    So, we can only capture 25 samples during 1000us (1ms==1KHz Pilot Signal)

  • 0 in reply to Aashiv Vij
    TI__Guru 63125 points

    That would be true if you configure eight continuous steps, where each step performs a measurement on one of the eight inputs. However, they may want to consider other configuration options.

    They could achieve 100ksps on one input, 25ksps on another input, and 12.5ksps on the other six inputs by configuring all sixteen steps. Every other step could be configured to performing a measurement on the 100ksps input, two steps of the other eight steps that are eight steps apart can be configured to perform a measurement on the 25ksps input, and each of the other six steps would be configured to perform a measurement on the other six 12.5ksps inputs.

    This is just one example of how the sixteen steps could be configured to increase the sample rate on some inputs at the cost of reducing sample rate on other inputs. The ADC steps are completely configurable, so there may be other options that would work for their application.

    Regards,
    Paul