Part Number: TDA4VM
Hi, Ti memenbers,
I get some trouble when I trying to enable SERDES0 LAN0 as SGMII.
Our custom board has two TDA4VM, we use the SGMII to connecte with Marvell's 88Q5072.
Our targe is enable the TDA4VM's SGMII port so that we can communicate with the Marvell's switch.
I will implemented the target with following two steps:
Sterp 1: Enable the SERDES0 LAN0 MAC to MAC(FORCEDLINK, 1Gbps, DUPLEX_FULL) on Ti''s EVM boards first, because we have two TDA4VM EVM boards and a PCIE cable.
Step 2: Debug the SGMII FORCEDLINK mode with Marvell's 88Q5072.on our custom board.
But I got some trouble when I try to implent Step 1. I'll get some detail informations following:
1. Software enviroment
- PSDKRA - V07.00.00.11
- PSDKLA - V07.00.00.04
2. I had got a referfence from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/936840/faq-dra829vxevm-is-it-possible-to-connect-two-dra829-evms-via-sgmii
Our custom board conected two TDA4 with SERDES1 LAN0 (TX, RX swaped), So I can verify this SGMII MAC to MAC demo on our board with following patch.
./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/environment/ti/k3_rproc.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/environment/ti/mmc.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/configs/tisdk_j7-evm_defconfig.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/rpmsg-kdrv/rpmsg_kdrv_switch.c.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c.ORIG ./do.env.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethfw/src/ethfw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethremotecfg/client/src/remote_device_client_ethswitch.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/do.mk.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/ethfw/src/app_ethfw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss_j721e.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss_defaults.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_init.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/common/dss_init.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlExtended.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlApi.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_board_pinmux.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/cpsw_mcm.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c.ORIG
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile 2021-05-20 13:27:18.416225880 +0800
@@ -106,17 +106,17 @@
u-boot-spl_clean: u-boot_clean
u-boot-spl_install: u-boot_install
-UBOOT_A53_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/a53
+UBOOT_A53_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/a72
UBOOT_R5_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/r5
UBOOT_ATF=$(TI_SDK_PATH)/board-support/prebuilt-images/bl31.bin
UBOOT_TEE=$(TI_SDK_PATH)/board-support/prebuilt-images/bl32.bin
UBOOT_SYSFW=$(TI_SDK_PATH)/board-support/prebuilt-images/sysfw.bin
-u-boot: u-boot-a53 u-boot-r5
-u-boot_clean: u-boot-a53_clean u-boot-r5_clean
+u-boot: u-boot-a72 u-boot-r5
+u-boot_clean: u-boot-a72_clean u-boot-r5_clean
-u-boot-a53:
+u-boot-a72:
@echo ===================================
@echo Building U-boot for A53
@echo ===================================
@@ -127,7 +127,7 @@
ATF=$(UBOOT_ATF) TEE=$(UBOOT_TEE) \
O=$(UBOOT_A53_BUILD_DIR)
-u-boot-a53_clean:
+u-boot-a72_clean:
@echo ===================================
@echo Cleaining U-boot for A53
@echo ===================================
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,4 @@
+#!/bin/bash
+make u-boot -j8
+make linux -j8
+make linux_install DESTDIR=${PSDKRA_PATH}/targetfs
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make 2021-05-20 13:27:18.420225905 +0800
@@ -45,7 +45,7 @@
EXEC_DIR ?=__EXEC_DIR__
# Add CROSS_COMPILE and UBOOT_MACHINE for the R5
-export CROSS_COMPILE_ARMV7=$(LINUX_DEVKIT_PATH)/sysroots/x86_64-arago-linux/usr/bin/arm-linux-gnueabihf-
+export CROSS_COMPILE_ARMV7=$(LINUX_DEVKIT_PATH)/sysroots/x86_64-arago-linux/usr/bin/arm-none-linux-gnueabihf-
UBOOT_MACHINE_R5=j721e_evm_r5_config
MAKE_JOBS=8
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts 2021-05-21 15:00:51.477251019 +0800
@@ -285,8 +285,7 @@
};
&serdes_ln_ctrl {
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -305,3 +304,13 @@
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
};
};
+
+&main_i2c0 {
+ /* disable main_i2c0 */
+ status = "disabled";
+};
+
+&main_i2c1 {
+ /* disable main_i2c1 */
+ status = "disabled";
+};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi 2021-05-21 15:00:37.141164391 +0800
@@ -31,14 +31,12 @@
serdes_ln_ctrl: serdes_ln_ctrl@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ mux-reg-masks = <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -381,14 +379,7 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
- sdhci-caps-mask = <0x2 0x0>;
dma-coherent;
};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h 2021-05-20 13:27:18.416225880 +0800
@@ -89,7 +89,7 @@
"bootpart=1:2\0" \
"bootdir=/boot\0" \
"mainr5f0_0loadaddr=88000000\0" \
- "mainr5f0_0fwname=/lib/firmware/j7-main-r5f0_0-fw\0" \
+ "mainr5f0_0fwname=/lib/firmware/j7-main-r5f0_0-fw-disable\0" \
"mcur5f0_0loadaddr=89000000\0" \
"mcur5f0_0fwname=/lib/firmware/j7-mcu-r5f0_0-fw\0" \
"rd_spec=-\0" \
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2021-05-21 15:27:22.962985721 +0800
@@ -254,6 +254,8 @@
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ J721E_IOPAD(0x178, PIN_INPUT, 3) /* (U27) UART6_RXD */
+ J721E_IOPAD(0x17C, PIN_OUTPUT, 3) /* (U24) UART6_TXD */
>;
};
@@ -766,8 +768,6 @@
&main_sdhci1 {
/* SD/MMC */
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
@@ -820,6 +820,7 @@
phys = <&serdes1_pcie_link>;
phy-names = "pcie_phy";
num-lanes = <2>;
+ status = "disabled";
};
&pcie2_rc {
@@ -864,7 +865,6 @@
&serdes_ln_ctrl {
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -909,7 +909,31 @@
maximum-speed = "high-speed";
};
+&reserved_memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ vision_apps_memory_region: vision_apps-dma-memory@ac000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xac000000 0x00 0x02000000>;
+ no-map;
+ };
+ vision_apps_shared_region: vision_apps_shared-memories {
+ compatible = "dma-heap-carveout";
+ reg = <0x00 0xae000000 0x00 0x20000000>;
+ };
+ vision_apps_core_heaps: vision_apps-core-heap-memory@ce000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xce000000 0x00 0x2d000000>;
+ no-map;
+ };
+};
+
/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
&main_uart2 {
status = "disabled";
};
+
+&serdes_wiz1 {
+ status = "disabled";
+};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2021-05-21 15:27:22.962985721 +0800
@@ -54,13 +54,11 @@
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -1645,16 +1643,9 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
- sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c 2021-05-20 13:27:18.420225905 +0800
@@ -31,8 +31,8 @@
#define VIRT_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
/* Number of TX/RX descriptors */
-#define VIRT_CPSW_MAX_TX_DESC 256
-#define VIRT_CPSW_MAX_RX_DESC 256
+#define VIRT_CPSW_MAX_TX_DESC 500
+#define VIRT_CPSW_MAX_RX_DESC 500
#define VIRT_CPSW_NAV_PS_DATA_SIZE 16
#define VIRT_CPSW_NAV_SW_DATA_SIZE 16
--- ./do.env.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./do.env 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,23 @@
+#!/bin/bash
+export PSDKLA_PATH=$PWD/ti-processor-sdk-linux-automotive-j7-evm-07_00_00
+export PSDKRA_PATH=$PWD/psdk_rtos_auto_j7_07_00_00_11
+
+#cp ${PSDKLA_PATH}/board-support/prebuilt-images/boot-j7-evm.tar.gz ${PSDKRA_PATH}/
+#cp ${PSDKLA_PATH}/filesystem/tisdk-default-image-j7-evm.tar.xz ${PSDKRA_PATH}/
+#cd $PSDKRA_PATH
+#./psdk_rtos_auto/scripts/setup_psdk_rtos_auto.sh
+#
+##To set the "wget" proxy
+#echo http_proxy=http://webproxy.ext.ti.com:80 > /.wgetrc
+#echo https_proxy=http://webproxy.ext.ti.com:80 >> /.wgetrc
+#echo ftp_proxy=http://webproxy.ext.ti.com:80 >> /.wgetrc
+#echo noproxy=ti.com >> /.wgetrc
+
+#Setup HTTP proxy
+#export HTTPS_PROXY=http://webproxy.ext.ti.com:80
+#export https_proxy=http://webproxy.ext.ti.com:80
+#export HTTP_PROXY=http://webproxy.ext.ti.com:80
+#export http_proxy=http://webproxy.ext.ti.com:80
+#export ftp_proxy=http://webproxy.ext.ti.com:80
+#export FTP_PROXY=http://webproxy.ext.ti.com:80
+#export no_proxy=ti.com
--- ./psdk_rtos_auto_j7_07_00_00_11/do.mk.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/do.mk 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,7 @@
+#!/bin/bash
+cd vision_apps
+#make -s pdk ethfw vision_apps
+make -s sdk
+make ethfw vision_apps
+#make -s pdk ethfw vision_apps BUILD_EMULATION_MODE=no BUILD_TARGET_MODE=yes BUILD_LINUX_A72=yes PROFILE=release -j8
+make linux_fs_install
--- ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h.ORIG 2020-06-20 02:44:12.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h 2021-05-20 13:27:18.420225905 +0800
@@ -90,9 +90,9 @@
#undef ENABLE_DSS_DUAL
/* define below to enable eDP display, make sure to undef ENABLE_DSS_HDMI & ENABLE_DSS_DSI as well */
-#define ENABLE_DSS_EDP
+#undef ENABLE_DSS_EDP
/* define below to enable HDMI display, make sure to undef ENABLE_DSS_EDP & ENABLE_DSS_DSI as well */
-#undef ENABLE_DSS_HDMI
+#define ENABLE_DSS_HDMI
/* define below to enable DSI display, make sure to undef ENABLE_DSS_HDMI & ENABLE_DSS_EDP as well */
#undef ENABLE_DSS_DSI
--- ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg.ORIG 2020-06-20 02:44:12.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg 2021-05-21 15:52:20.024891886 +0800
@@ -63,7 +63,7 @@
/* ================ General configuration ================ */
function init(ndkCfgArg)
{
- var enableStaticIP = 0;
+ var enableStaticIP = 1;
var enableTelnet = 1;
/* NDK modules */
@@ -132,7 +132,7 @@
Ip.ResolveIP = false;
Ip.CallByIP = false;
Ip.autoIp = false;
- Ip.address = "192.168.1.203";
+ Ip.address = "192.168.1.204";
Ip.mask = "255.255.255.0";
Ip.gatewayIpAddr = "192.168.1.1";
}
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c 2021-05-21 13:26:36.987252807 +0800
@@ -1540,7 +1540,7 @@
{
CSL_SGMII_getStatus(hPort->sgmiiRegs, hPort->portNum, &sgmiiStatus);
}
- while (sgmiiStatus.bIsLinkUp);
+ while (1U != sgmiiStatus.bIsLinkUp);
status = CPSW_SOK;
}
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h 2021-05-20 13:27:18.420225905 +0800
@@ -88,7 +88,7 @@
#define ENET_CTRL_RGMII_ID_INTTXDLY (0U)
#define ENET_CTRL_RGMII_ID_NODELAY (1U)
-#define CPSW_UTILS_MCU2_0_UART_INSTANCE (2U)
+#define CPSW_UTILS_MCU2_0_UART_INSTANCE (6U)
#if defined(__KLOCWORK__)
#define CpswAppUtils_assert(cond) do { if (!(cond)) abort(); } while (0)
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c 2021-05-21 15:52:20.024891886 +0800
@@ -61,6 +61,7 @@
#include <ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h>
#include <ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_appboardutils.h>
+//#define CONFIG_MASTER_BOARD 1
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
@@ -215,7 +216,7 @@
uint32_t clkModuleId[] = { TISCI_DEV_DDR0,
TISCI_DEV_TIMER12,
TISCI_DEV_TIMER13,
- TISCI_DEV_UART2, };
+ TISCI_DEV_UART6, };
appFlags = 0U;
moduleCnt = CPSW_UTILS_ARRAYSIZE(clkModuleId);
@@ -234,10 +235,12 @@
status = CpswAppBoardUtils_configEthFwPinmux();
CpswAppUtils_assert(status == BOARD_SOK);
-#ifndef SDK_6_2_CORE_SDK_IMAGE
#if defined(BUILD_MCU2_0)
CpswAppBoardUtils_configSerdesClks();
+#endif
+#ifndef SDK_6_2_CORE_SDK_IMAGE
+#if defined(BUILD_MCU2_0)
/* Configure SGMII/QSGMII expansion board
* Note - We call below without any check as these functions can be called without daughter board also.
* They just change the output state of IO expander pins on CP board which goes to daughter board.
@@ -402,25 +405,29 @@
{
Board_STATUS boardStatus;
- CpswAppUtils_assert(portNum == CPSW_MAC_PORT_1);
+ CpswAppUtils_assert(portNum == CPSW_MAC_PORT_2);
/* Override the ENET control set by board lib */
boardStatus = Board_cpsw9gEthConfig(portNum, SGMII);
CpswAppUtils_assert(boardStatus == BOARD_SOK);
- boardStatus = Board_serdesCfgSgmii();
+ boardStatus = Board_serdesCfgSgmii_serdes1();
CpswAppUtils_assert(boardStatus == BOARD_SOK);
Cpsw_initPhyParams(phyConfig);
- phyConfig->phyAddr = CpswAppBoardUtils_getSgmiiPhyAddr();
- phyConfig->skipExtendedConfig = true;
+ phyConfig->phyAddr = CPSW_PHY_INVALID_PHYADDR;
/* RGMII interface type */
interface->layerType = CPSW_MAC_LAYER_GMII;
interface->sublayerType = CPSW_MAC_SUBLAYER_SERIAL;
interface->variantType = CPSW_MAC_VARIANT_NONE;
- macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_WITH_PHY;
+#ifdef CONFIG_MASTER_BOARD
+ macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER;
+#else //CONFIG_MASTER_BOARD
+ macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE;
+#endif //CONFIG_MASTER_BOARD
+ macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_FORCEDLINK;
}
void CpswAppBoardUtils_setPhyConfigQsgmii(Cpsw_Type cpswType,
@@ -569,7 +576,6 @@
case CPSW_9G:
if ( CPSW_MAC_PORT_0 == portNum ||
- CPSW_MAC_PORT_2 == portNum ||
CPSW_MAC_PORT_3 == portNum ||
CPSW_MAC_PORT_7 == portNum )
{
@@ -579,6 +585,13 @@
interface,
phyConfig);
}
+ else if (CPSW_MAC_PORT_2 == portNum)
+ {
+ CpswAppBoardUtils_setPhyConfigSgmii(portNum,
+ macConfig,
+ interface,
+ phyConfig);
+ }
else
{
CpswAppBoardUtils_setPhyConfigQsgmii(cpswType,
@@ -703,6 +716,7 @@
* addresses in Linux builds. For RTOS build, MAC addresses will still
* be read from EEPROM as such I2C contention isn't an problem.
*/
+#ifdef CONFIG_MASTER_BOARD
uint8_t macAddrBuf[][CPSW_MAC_ADDR_LEN] =
{
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC1U },
@@ -715,6 +729,20 @@
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xC6U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xC7U },
};
+#else //CONFIG_MASTER_BOARD
+ uint8_t macAddrBuf[][CPSW_MAC_ADDR_LEN] =
+ {
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB1U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB2U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB3U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB4U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB5U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB4U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB5U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB6U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB7U },
+ };
+#endif //CONFIG_MASTER_BOARD
uint32_t macAddrCnt = CPSWAPPUTILS_ARRAY_SIZE(macAddrBuf);
/* Save only those required to meet the max number of MAC entries */
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c 2021-05-20 17:47:10.351431709 +0800
@@ -496,8 +496,8 @@
interface,
phyConfig);
- linkConfig->speed = CPSW_SPEED_AUTO;
- linkConfig->duplexity = CPSW_DUPLEX_AUTO;
+ linkConfig->speed = CPSW_SPEED_1GBI; //CPSW_SPEED_1GBI; CPSW_SPEED_100MBIT
+ linkConfig->duplexity = CPSW_DUPLEX_FULL;
}
static void CpswNimuApp_portLinkStatusChangeCb(Cpsw_MacPort portNum,
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c 2021-05-20 13:27:18.420225905 +0800
@@ -88,29 +88,7 @@
*/
static Board_STATUS Board_setHDMIMux(void)
{
- Board_IoExpCfg_t ioExpCfg;
- Board_STATUS status;
-
- ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;
- ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
- ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE1_ADDR;
- ioExpCfg.enableIntr = false;
- ioExpCfg.ioExpType = TWO_PORT_IOEXP;
- ioExpCfg.portNum = PORTNUM_1;
- ioExpCfg.pinNum = PIN_NUM_4;
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;
-
- status = Board_setIoExpPinOutput(&ioExpCfg);
- if(status != BOARD_SOK)
- {
- return status;
- }
-
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
- ioExpCfg.pinNum = PIN_NUM_5;
- status = Board_setIoExpPinOutput(&ioExpCfg);
-
- return status;
+ return 0;
}
/**
@@ -121,21 +99,7 @@
*/
static Board_STATUS Board_setHDMIPdHigh(void)
{
- Board_IoExpCfg_t ioExpCfg;
- Board_STATUS status;
-
- ioExpCfg.i2cInst = BOARD_HDMI_IO_EXP_INSTANCE;
- ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
- ioExpCfg.slaveAddr = BOARD_HDMI_IO_SLAVE_ADDR;
- ioExpCfg.enableIntr = false;
- ioExpCfg.ioExpType = TWO_PORT_IOEXP;
- ioExpCfg.portNum = PORTNUM_1;
- ioExpCfg.pinNum = PIN_NUM_0;
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
-
- status = Board_setIoExpPinOutput(&ioExpCfg);
-
- return status;
+ return 0;
}
/**
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c 2021-05-21 15:27:22.966985745 +0800
@@ -711,7 +711,6 @@
for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
if ( 0U == portNum ||
- 2U == portNum ||
3U == portNum ||
7U == portNum )
{
@@ -723,6 +722,10 @@
{
status = Board_cpsw9gEthConfig(portNum, QSGMII);
}
+ else if (2U == portNum)
+ {
+ status = Board_cpsw9gEthConfig(portNum, SGMII);
+ }
else
{
status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h 2021-05-21 15:27:22.966985745 +0800
@@ -85,6 +85,7 @@
*
*/
Board_STATUS Board_serdesCfgSgmii(void);
+Board_STATUS Board_serdesCfgSgmii_serdes1(void);
/**
* \brief serdes configurations for Sierra 1 in QSGMII mode
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c 2021-05-21 15:27:22.966985745 +0800
@@ -111,6 +111,76 @@
return BOARD_SOK;
}
+static Board_STATUS Board_CfgSgmii_serdes1(void)
+{
+ CSL_SerdesResult result;
+ CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
+
+ memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
+
+ /* SGMII Config */
+ serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_SIERRA_SERDES1;
+ serdesLane0EnableParams.baseAddr = CSL_SERDES_16G1_BASE;
+ serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
+ serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
+ serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
+ serdesLane0EnableParams.numLanes = 0x2;
+ serdesLane0EnableParams.laneMask = 0x3;
+ serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
+ serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
+ serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
+ serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
+
+ serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
+
+ /* Select the IP type, IP instance num, Serdes Lane Number */
+ CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.phyType,
+ serdesLane0EnableParams.phyInstanceNum,
+ serdesLane0EnableParams.serdesInstance,
+ 2U);
+
+
+ result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.baseAddr,
+ serdesLane0EnableParams.refClock,
+ serdesLane0EnableParams.refClkSrc,
+ serdesLane0EnableParams.serdesInstance,
+ serdesLane0EnableParams.phyType);
+
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+ /* Assert PHY reset and disable all lanes */
+ CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
+
+ /* Load the Serdes Config File */
+ result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
+ /* Return error if input params are invalid */
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+
+ /* Common Lane Enable API for lane enable, pll enable etc */
+ laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
+ if (laneRetVal != 0)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
static Board_STATUS Board_CfgQsgmii(void)
{
CSL_SerdesResult result;
@@ -179,6 +249,20 @@
}
return BOARD_SOK;
+}
+
+Board_STATUS Board_serdesCfgSgmii_serdes1(void)
+{
+ Board_STATUS ret;
+
+ /* SERDES0 Initializations */
+ ret = Board_CfgSgmii_serdes1();
+ if(ret != BOARD_SOK)
+ {
+ return ret;
+ }
+
+ return BOARD_SOK;
}
/**
3. when I try to change the SGMII from SDESE1 LAN0 to SERDE0 LAN0, It' can linkup. the following path is the patch for SGMII SERDES0 LAN0(FORCEDLINK, 1Gbps, DUPLEX_FULL)
./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/environment/ti/k3_rproc.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/environment/ti/mmc.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/configs/tisdk_j7-evm_defconfig.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/rpmsg-kdrv/rpmsg_kdrv_switch.c.ORIG ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c.ORIG ./do.env.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethfw/src/ethfw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethremotecfg/server/src/cpsw_proxy_server.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/ethremotecfg/client/src/remote_device_client_ethswitch.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/ethfw/apps/app_remoteswitchcfg_server/mcu_2_0/main_tirtos.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/do.mk.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/ethfw/src/app_ethfw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss_j721e.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss_defaults.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/dss/src/app_dss.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_init.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/common/dss_init.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlExtended.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlApi.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_board_pinmux.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/cpsw_mcm.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h.ORIG ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c.ORIG
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Makefile 2021-05-20 13:27:18.416225880 +0800
@@ -106,17 +106,17 @@
u-boot-spl_clean: u-boot_clean
u-boot-spl_install: u-boot_install
-UBOOT_A53_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/a53
+UBOOT_A53_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/a72
UBOOT_R5_BUILD_DIR=$(TI_SDK_PATH)/board-support/u-boot_build/r5
UBOOT_ATF=$(TI_SDK_PATH)/board-support/prebuilt-images/bl31.bin
UBOOT_TEE=$(TI_SDK_PATH)/board-support/prebuilt-images/bl32.bin
UBOOT_SYSFW=$(TI_SDK_PATH)/board-support/prebuilt-images/sysfw.bin
-u-boot: u-boot-a53 u-boot-r5
-u-boot_clean: u-boot-a53_clean u-boot-r5_clean
+u-boot: u-boot-a72 u-boot-r5
+u-boot_clean: u-boot-a72_clean u-boot-r5_clean
-u-boot-a53:
+u-boot-a72:
@echo ===================================
@echo Building U-boot for A53
@echo ===================================
@@ -127,7 +127,7 @@
ATF=$(UBOOT_ATF) TEE=$(UBOOT_TEE) \
O=$(UBOOT_A53_BUILD_DIR)
-u-boot-a53_clean:
+u-boot-a72_clean:
@echo ===================================
@echo Cleaining U-boot for A53
@echo ===================================
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/do.mk 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,4 @@
+#!/bin/bash
+make u-boot -j8
+make linux -j8
+make linux_install DESTDIR=${PSDKRA_PATH}/targetfs
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/Rules.make 2021-05-20 13:27:18.420225905 +0800
@@ -45,7 +45,7 @@
EXEC_DIR ?=__EXEC_DIR__
# Add CROSS_COMPILE and UBOOT_MACHINE for the R5
-export CROSS_COMPILE_ARMV7=$(LINUX_DEVKIT_PATH)/sysroots/x86_64-arago-linux/usr/bin/arm-linux-gnueabihf-
+export CROSS_COMPILE_ARMV7=$(LINUX_DEVKIT_PATH)/sysroots/x86_64-arago-linux/usr/bin/arm-none-linux-gnueabihf-
UBOOT_MACHINE_R5=j721e_evm_r5_config
MAKE_JOBS=8
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-common-proc-board.dts 2021-05-20 13:27:18.416225880 +0800
@@ -305,3 +305,13 @@
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
};
};
+
+&main_i2c0 {
+ /* disable main_i2c0 */
+ status = "disabled";
+};
+
+&main_i2c1 {
+ /* disable main_i2c1 */
+ status = "disabled";
+};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi.ORIG 2021-05-18 11:17:41.933138501 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/arch/arm/dts/k3-j721e-main.dtsi 2021-05-20 13:27:18.416225880 +0800
@@ -381,14 +381,7 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
- sdhci-caps-mask = <0x2 0x0>;
dma-coherent;
};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/u-boot-2020.01+gitAUTOINC+f9b0d030d3-gf9b0d030d3/include/configs/j721e_evm.h 2021-05-20 13:27:18.416225880 +0800
@@ -89,7 +89,7 @@
"bootpart=1:2\0" \
"bootdir=/boot\0" \
"mainr5f0_0loadaddr=88000000\0" \
- "mainr5f0_0fwname=/lib/firmware/j7-main-r5f0_0-fw\0" \
+ "mainr5f0_0fwname=/lib/firmware/j7-main-r5f0_0-fw-disable\0" \
"mcur5f0_0loadaddr=89000000\0" \
"mcur5f0_0fwname=/lib/firmware/j7-mcu-r5f0_0-fw\0" \
"rd_spec=-\0" \
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2021-05-21 13:26:36.983252782 +0800
@@ -254,6 +254,8 @@
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
+ J721E_IOPAD(0x178, PIN_INPUT, 3) /* (U27) UART6_RXD */
+ J721E_IOPAD(0x17C, PIN_OUTPUT, 3) /* (U24) UART6_TXD */
>;
};
@@ -766,8 +768,6 @@
&main_sdhci1 {
/* SD/MMC */
- vmmc-supply = <&vdd_mmc1>;
- vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
disable-wp;
@@ -813,6 +813,7 @@
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
num-lanes = <1>;
+ status = "disabled";
};
&pcie1_rc {
@@ -820,6 +821,7 @@
phys = <&serdes1_pcie_link>;
phy-names = "pcie_phy";
num-lanes = <2>;
+ status = "disabled";
};
&pcie2_rc {
@@ -827,6 +829,7 @@
phys = <&serdes2_pcie_link>;
phy-names = "pcie_phy";
num-lanes = <2>;
+ status = "disabled";
};
&pcie0_ep {
@@ -863,8 +866,7 @@
};
&serdes_ln_ctrl {
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -909,7 +911,31 @@
maximum-speed = "high-speed";
};
+&reserved_memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ vision_apps_memory_region: vision_apps-dma-memory@ac000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xac000000 0x00 0x02000000>;
+ no-map;
+ };
+ vision_apps_shared_region: vision_apps_shared-memories {
+ compatible = "dma-heap-carveout";
+ reg = <0x00 0xae000000 0x00 0x20000000>;
+ };
+ vision_apps_core_heaps: vision_apps-core-heap-memory@ce000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xce000000 0x00 0x2d000000>;
+ no-map;
+ };
+};
+
/* uart2 assigned to cpsw9g eth-switch fw running on remote CPU core */
&main_uart2 {
status = "disabled";
};
+
+&serdes_wiz0 {
+ status = "disabled";
+};
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2021-05-21 13:26:36.983252782 +0800
@@ -53,14 +53,12 @@
serdes_ln_ctrl: serdes_ln_ctrl@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ mux-reg-masks = <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
@@ -1645,16 +1643,9 @@
assigned-clocks = <&k3_clks 92 0>;
assigned-clock-parents = <&k3_clks 92 1>;
ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-sd-hs = <0xf>;
- ti,otap-del-sel-sdr12 = <0xf>;
- ti,otap-del-sel-sdr25 = <0xf>;
- ti,otap-del-sel-sdr50 = <0xc>;
- ti,otap-del-sel-sdr104 = <0x5>;
- ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
- sdhci-caps-mask = <0x2 0x0>;
};
main_sdhci2: sdhci@4f98000 {
--- ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./ti-processor-sdk-linux-automotive-j7-evm-07_00_00/board-support/linux-5.4.40+gitAUTOINC+66cf445b76-g66cf445b76/drivers/net/ethernet/ti/j721e-cpsw-virt-mac.c 2021-05-20 13:27:18.420225905 +0800
@@ -31,8 +31,8 @@
#define VIRT_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
/* Number of TX/RX descriptors */
-#define VIRT_CPSW_MAX_TX_DESC 256
-#define VIRT_CPSW_MAX_RX_DESC 256
+#define VIRT_CPSW_MAX_TX_DESC 500
+#define VIRT_CPSW_MAX_RX_DESC 500
#define VIRT_CPSW_NAV_PS_DATA_SIZE 16
#define VIRT_CPSW_NAV_SW_DATA_SIZE 16
--- ./do.env.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./do.env 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,23 @@
+#!/bin/bash
+export PSDKLA_PATH=$PWD/ti-processor-sdk-linux-automotive-j7-evm-07_00_00
+export PSDKRA_PATH=$PWD/psdk_rtos_auto_j7_07_00_00_11
+
+#cp ${PSDKLA_PATH}/board-support/prebuilt-images/boot-j7-evm.tar.gz ${PSDKRA_PATH}/
+#cp ${PSDKLA_PATH}/filesystem/tisdk-default-image-j7-evm.tar.xz ${PSDKRA_PATH}/
+#cd $PSDKRA_PATH
+#./psdk_rtos_auto/scripts/setup_psdk_rtos_auto.sh
+#
+##To set the "wget" proxy
+#echo http_proxy=http://webproxy.ext.ti.com:80 > /.wgetrc
+#echo https_proxy=http://webproxy.ext.ti.com:80 >> /.wgetrc
+#echo ftp_proxy=http://webproxy.ext.ti.com:80 >> /.wgetrc
+#echo noproxy=ti.com >> /.wgetrc
+
+#Setup HTTP proxy
+#export HTTPS_PROXY=http://webproxy.ext.ti.com:80
+#export https_proxy=http://webproxy.ext.ti.com:80
+#export HTTP_PROXY=http://webproxy.ext.ti.com:80
+#export http_proxy=http://webproxy.ext.ti.com:80
+#export ftp_proxy=http://webproxy.ext.ti.com:80
+#export FTP_PROXY=http://webproxy.ext.ti.com:80
+#export no_proxy=ti.com
--- ./psdk_rtos_auto_j7_07_00_00_11/do.mk.ORIG 2021-05-18 11:17:41.937138526 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/do.mk 2021-05-20 13:27:18.420225905 +0800
@@ -0,0 +1,7 @@
+#!/bin/bash
+cd vision_apps
+#make -s pdk ethfw vision_apps
+make -s sdk
+make ethfw vision_apps
+#make -s pdk ethfw vision_apps BUILD_EMULATION_MODE=no BUILD_TARGET_MODE=yes BUILD_LINUX_A72=yes PROFILE=release -j8
+make linux_fs_install
--- ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/ethfw/src/app_ethfw.c.ORIG 2020-06-20 02:44:13.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/utils/ethfw/src/app_ethfw.c 2021-05-21 13:27:17.067465468 +0800
@@ -79,40 +79,6 @@
.portNum = CPSW_MAC_PORT_0,
.vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U },
},
-#if defined(SOC_J721E)
- /* On J721E EVM to use all 8 ports simultaneously, we use below configuration
- RGMII Ports - 1,3,4,8. QSGMII ports - 2,5,6,7 */
- {
- .portNum = CPSW_MAC_PORT_2, /* RGMII */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
- {
- .portNum = CPSW_MAC_PORT_3, /* RGMII */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
- {
- .portNum = CPSW_MAC_PORT_7, /* RGMII */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
-#if defined(ENABLE_QSGMII_PORTS) //kept it disabled for 6.2
- {
- .portNum = CPSW_MAC_PORT_1, /* QSGMII main */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
- {
- .portNum = CPSW_MAC_PORT_4, /* QSGMII sub */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
- {
- .portNum = CPSW_MAC_PORT_5, /* QSGMII sub */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
- {
- .portNum = CPSW_MAC_PORT_6, /* QSGMII sub */
- .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
- },
-#endif
-#endif
};
static int32_t EthApp_initEthFw(void);
--- ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h.ORIG 2020-06-20 02:44:12.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/common/app_cfg_mcu2_0.h 2021-05-20 13:27:18.420225905 +0800
@@ -90,9 +90,9 @@
#undef ENABLE_DSS_DUAL
/* define below to enable eDP display, make sure to undef ENABLE_DSS_HDMI & ENABLE_DSS_DSI as well */
-#define ENABLE_DSS_EDP
+#undef ENABLE_DSS_EDP
/* define below to enable HDMI display, make sure to undef ENABLE_DSS_EDP & ENABLE_DSS_DSI as well */
-#undef ENABLE_DSS_HDMI
+#define ENABLE_DSS_HDMI
/* define below to enable DSI display, make sure to undef ENABLE_DSS_HDMI & ENABLE_DSS_EDP as well */
#undef ENABLE_DSS_DSI
--- ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg.ORIG 2020-06-20 02:44:12.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/vision_apps/apps/basic_demos/app_tirtos/bios_cfg/ndk.cfg 2021-05-21 13:31:08.200370456 +0800
@@ -63,7 +63,7 @@
/* ================ General configuration ================ */
function init(ndkCfgArg)
{
- var enableStaticIP = 0;
+ var enableStaticIP = 1;
var enableTelnet = 1;
/* NDK modules */
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/src/cpsw_macport.c 2021-05-21 13:26:36.987252807 +0800
@@ -1540,7 +1540,7 @@
{
CSL_SGMII_getStatus(hPort->sgmiiRegs, hPort->portNum, &sgmiiStatus);
}
- while (sgmiiStatus.bIsLinkUp);
+ while (1U != sgmiiStatus.bIsLinkUp);
status = CPSW_SOK;
}
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h 2021-05-20 13:27:18.420225905 +0800
@@ -88,7 +88,7 @@
#define ENET_CTRL_RGMII_ID_INTTXDLY (0U)
#define ENET_CTRL_RGMII_ID_NODELAY (1U)
-#define CPSW_UTILS_MCU2_0_UART_INSTANCE (2U)
+#define CPSW_UTILS_MCU2_0_UART_INSTANCE (6U)
#if defined(__KLOCWORK__)
#define CpswAppUtils_assert(cond) do { if (!(cond)) abort(); } while (0)
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_apputils/V1/cpsw_appboardutils_j721e_evm.c 2021-05-21 13:31:08.200370456 +0800
@@ -61,6 +61,7 @@
#include <ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_apputils.h>
#include <ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_appboardutils.h>
+#define CONFIG_MASTER_BOARD 1
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
@@ -215,7 +216,7 @@
uint32_t clkModuleId[] = { TISCI_DEV_DDR0,
TISCI_DEV_TIMER12,
TISCI_DEV_TIMER13,
- TISCI_DEV_UART2, };
+ TISCI_DEV_UART6, };
appFlags = 0U;
moduleCnt = CPSW_UTILS_ARRAYSIZE(clkModuleId);
@@ -234,10 +235,12 @@
status = CpswAppBoardUtils_configEthFwPinmux();
CpswAppUtils_assert(status == BOARD_SOK);
-#ifndef SDK_6_2_CORE_SDK_IMAGE
#if defined(BUILD_MCU2_0)
CpswAppBoardUtils_configSerdesClks();
+#endif
+#ifndef SDK_6_2_CORE_SDK_IMAGE
+#if defined(BUILD_MCU2_0)
/* Configure SGMII/QSGMII expansion board
* Note - We call below without any check as these functions can be called without daughter board also.
* They just change the output state of IO expander pins on CP board which goes to daughter board.
@@ -249,6 +252,7 @@
status = Board_serdesCfgQsgmii();
CpswAppUtils_assert(status == BOARD_SOK);
}
+
#endif
#endif
@@ -402,25 +406,29 @@
{
Board_STATUS boardStatus;
- CpswAppUtils_assert(portNum == CPSW_MAC_PORT_1);
+ CpswAppUtils_assert(portNum == CPSW_MAC_PORT_0);
/* Override the ENET control set by board lib */
boardStatus = Board_cpsw9gEthConfig(portNum, SGMII);
CpswAppUtils_assert(boardStatus == BOARD_SOK);
- boardStatus = Board_serdesCfgSgmii();
+ boardStatus = Board_serdesCfgSgmii_serdes0();
CpswAppUtils_assert(boardStatus == BOARD_SOK);
Cpsw_initPhyParams(phyConfig);
- phyConfig->phyAddr = CpswAppBoardUtils_getSgmiiPhyAddr();
- phyConfig->skipExtendedConfig = true;
+ phyConfig->phyAddr = CPSW_PHY_INVALID_PHYADDR;
/* RGMII interface type */
interface->layerType = CPSW_MAC_LAYER_GMII;
interface->sublayerType = CPSW_MAC_SUBLAYER_SERIAL;
interface->variantType = CPSW_MAC_VARIANT_NONE;
- macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_WITH_PHY;
+#ifdef CONFIG_MASTER_BOARD
+ macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER;
+#else //CONFIG_MASTER_BOARD
+ macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE;
+#endif //CONFIG_MASTER_BOARD
+ //macConfig->sgmiiConfig.sgmiiMode = CPSW_MAC_SGMIIMODE_SGMII_FORCEDLINK;
}
void CpswAppBoardUtils_setPhyConfigQsgmii(Cpsw_Type cpswType,
@@ -568,9 +576,7 @@
case CPSW_9G:
- if ( CPSW_MAC_PORT_0 == portNum ||
- CPSW_MAC_PORT_2 == portNum ||
- CPSW_MAC_PORT_3 == portNum ||
+ if ( CPSW_MAC_PORT_3 == portNum ||
CPSW_MAC_PORT_7 == portNum )
{
CpswAppBoardUtils_setPhyConfigRgmii(cpswType,
@@ -579,6 +585,14 @@
interface,
phyConfig);
}
+ else if ( CPSW_MAC_PORT_0 == portNum ||
+ CPSW_MAC_PORT_1 == portNum )
+ {
+ CpswAppBoardUtils_setPhyConfigSgmii(portNum,
+ macConfig,
+ interface,
+ phyConfig);
+ }
else
{
CpswAppBoardUtils_setPhyConfigQsgmii(cpswType,
@@ -703,6 +717,7 @@
* addresses in Linux builds. For RTOS build, MAC addresses will still
* be read from EEPROM as such I2C contention isn't an problem.
*/
+#ifdef CONFIG_MASTER_BOARD
uint8_t macAddrBuf[][CPSW_MAC_ADDR_LEN] =
{
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xC1U },
@@ -715,6 +730,20 @@
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xC6U },
{ 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xC7U },
};
+#else //CONFIG_MASTER_BOARD
+ uint8_t macAddrBuf[][CPSW_MAC_ADDR_LEN] =
+ {
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB1U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB2U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB3U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB4U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0x92U, 0xB5U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB4U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB5U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB6U },
+ { 0x70U, 0xFFU, 0x76U, 0x1DU, 0X8BU, 0xB7U },
+ };
+#endif //CONFIG_MASTER_BOARD
uint32_t macAddrCnt = CPSWAPPUTILS_ARRAY_SIZE(macAddrBuf);
/* Save only those required to meet the max number of MAC entries */
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c.ORIG 2020-06-20 02:44:37.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/drv/cpsw/examples/cpsw_nimu_example/main_tirtos.c 2021-05-20 17:47:10.351431709 +0800
@@ -496,8 +496,8 @@
interface,
phyConfig);
- linkConfig->speed = CPSW_SPEED_AUTO;
- linkConfig->duplexity = CPSW_DUPLEX_AUTO;
+ linkConfig->speed = CPSW_SPEED_1GBI; //CPSW_SPEED_1GBI; CPSW_SPEED_100MBIT
+ linkConfig->duplexity = CPSW_DUPLEX_FULL;
}
static void CpswNimuApp_portLinkStatusChangeCb(Cpsw_MacPort portNum,
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_control.c 2021-05-20 13:27:18.420225905 +0800
@@ -88,29 +88,7 @@
*/
static Board_STATUS Board_setHDMIMux(void)
{
- Board_IoExpCfg_t ioExpCfg;
- Board_STATUS status;
-
- ioExpCfg.i2cInst = BOARD_I2C_IOEXP_DEVICE1_INSTANCE;
- ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
- ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_DEVICE1_ADDR;
- ioExpCfg.enableIntr = false;
- ioExpCfg.ioExpType = TWO_PORT_IOEXP;
- ioExpCfg.portNum = PORTNUM_1;
- ioExpCfg.pinNum = PIN_NUM_4;
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_LOW;
-
- status = Board_setIoExpPinOutput(&ioExpCfg);
- if(status != BOARD_SOK)
- {
- return status;
- }
-
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
- ioExpCfg.pinNum = PIN_NUM_5;
- status = Board_setIoExpPinOutput(&ioExpCfg);
-
- return status;
+ return 0;
}
/**
@@ -121,21 +99,7 @@
*/
static Board_STATUS Board_setHDMIPdHigh(void)
{
- Board_IoExpCfg_t ioExpCfg;
- Board_STATUS status;
-
- ioExpCfg.i2cInst = BOARD_HDMI_IO_EXP_INSTANCE;
- ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
- ioExpCfg.slaveAddr = BOARD_HDMI_IO_SLAVE_ADDR;
- ioExpCfg.enableIntr = false;
- ioExpCfg.ioExpType = TWO_PORT_IOEXP;
- ioExpCfg.portNum = PORTNUM_1;
- ioExpCfg.pinNum = PIN_NUM_0;
- ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
-
- status = Board_setIoExpPinOutput(&ioExpCfg);
-
- return status;
+ return 0;
}
/**
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_ethernet_config.c 2021-05-21 13:26:36.987252807 +0800
@@ -710,19 +710,21 @@
/* Configures the CPSW9G RGMII ports */
for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
- if ( 0U == portNum ||
- 2U == portNum ||
- 3U == portNum ||
+ if ( 3U == portNum ||
7U == portNum )
{
status = Board_cpsw9gEthConfig(portNum, RGMII);
}
else
{
- if (1U == portNum)
+ if (2U == portNum)
{
status = Board_cpsw9gEthConfig(portNum, QSGMII);
}
+ else if ((0U == portNum) || (1U == portNum))
+ {
+ status = Board_cpsw9gEthConfig(portNum, SGMII);
+ }
else
{
status = Board_cpsw9gEthConfig(portNum, QSGMII_SUB);
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h 2021-05-21 13:26:36.987252807 +0800
@@ -85,6 +85,8 @@
*
*/
Board_STATUS Board_serdesCfgSgmii(void);
+Board_STATUS Board_serdesCfgSgmii_serdes0(void);
+Board_STATUS Board_serdesCfgSgmii_serdes1(void);
/**
* \brief serdes configurations for Sierra 1 in QSGMII mode
--- ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c.ORIG 2020-06-20 02:44:28.000000000 +0800
+++ ./psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/board/src/j721e_evm/board_serdes_cfg.c 2021-05-21 13:29:29.795958525 +0800
@@ -111,6 +111,146 @@
return BOARD_SOK;
}
+static Board_STATUS Board_CfgSgmii_serdes0(void)
+{
+ CSL_SerdesResult result;
+ CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
+
+ memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
+
+ /* SGMII Config */
+ serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_SIERRA_SERDES0;
+ serdesLane0EnableParams.baseAddr = CSL_SERDES_16G0_BASE;
+ serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
+ serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
+ serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
+ serdesLane0EnableParams.numLanes = 0x2;
+ serdesLane0EnableParams.laneMask = 0x3;
+ serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
+ serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
+ serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
+ serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
+
+ serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
+
+ /* Select the IP type, IP instance num, Serdes Lane Number */
+ CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.phyType,
+ serdesLane0EnableParams.phyInstanceNum,
+ serdesLane0EnableParams.serdesInstance,
+ 0U);
+
+
+ result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.baseAddr,
+ serdesLane0EnableParams.refClock,
+ serdesLane0EnableParams.refClkSrc,
+ serdesLane0EnableParams.serdesInstance,
+ serdesLane0EnableParams.phyType);
+
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+ /* Assert PHY reset and disable all lanes */
+ CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
+
+ /* Load the Serdes Config File */
+ result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
+ /* Return error if input params are invalid */
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+
+ /* Common Lane Enable API for lane enable, pll enable etc */
+ laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
+ if (laneRetVal != 0)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
+static Board_STATUS Board_CfgSgmii_serdes1(void)
+{
+ CSL_SerdesResult result;
+ CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
+ CSL_SerdesLaneEnableParams serdesLane0EnableParams = {0};
+
+ memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));
+
+ /* SGMII Config */
+ serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance)CSL_SIERRA_SERDES1;
+ serdesLane0EnableParams.baseAddr = CSL_SERDES_16G1_BASE;
+ serdesLane0EnableParams.refClock = CSL_SERDES_REF_CLOCK_100M;
+ serdesLane0EnableParams.refClkSrc = CSL_SERDES_REF_CLOCK_INT;
+ serdesLane0EnableParams.linkRate = CSL_SERDES_LINK_RATE_1p25G;
+ serdesLane0EnableParams.numLanes = 0x2;
+ serdesLane0EnableParams.laneMask = 0x3;
+ serdesLane0EnableParams.SSC_mode = CSL_SERDES_NO_SSC;
+ serdesLane0EnableParams.phyType = CSL_SERDES_PHY_TYPE_SGMII;
+ serdesLane0EnableParams.operatingMode = CSL_SERDES_FUNCTIONAL_MODE;
+ serdesLane0EnableParams.phyInstanceNum = SERDES_LANE_SELECT_CPSW;
+ serdesLane0EnableParams.pcieGenType = CSL_SERDES_PCIE_GEN3;
+
+ serdesLane0EnableParams.laneCtrlRate[0] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[0] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ serdesLane0EnableParams.laneCtrlRate[1] = CSL_SERDES_LANE_FULL_RATE;
+ serdesLane0EnableParams.loopbackMode[1] = CSL_SERDES_LOOPBACK_DISABLED;
+
+ CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);
+
+ /* Select the IP type, IP instance num, Serdes Lane Number */
+ CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.phyType,
+ serdesLane0EnableParams.phyInstanceNum,
+ serdesLane0EnableParams.serdesInstance,
+ 2U);
+
+
+ result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
+ serdesLane0EnableParams.baseAddr,
+ serdesLane0EnableParams.refClock,
+ serdesLane0EnableParams.refClkSrc,
+ serdesLane0EnableParams.serdesInstance,
+ serdesLane0EnableParams.phyType);
+
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+ /* Assert PHY reset and disable all lanes */
+ CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);
+
+ /* Load the Serdes Config File */
+ result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
+ /* Return error if input params are invalid */
+ if (result != CSL_SERDES_NO_ERR)
+ {
+ return BOARD_FAIL;
+ }
+
+ /* Common Lane Enable API for lane enable, pll enable etc */
+ laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
+ if (laneRetVal != 0)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
static Board_STATUS Board_CfgQsgmii(void)
{
CSL_SerdesResult result;
@@ -179,6 +319,34 @@
}
return BOARD_SOK;
+}
+
+Board_STATUS Board_serdesCfgSgmii_serdes0(void)
+{
+ Board_STATUS ret;
+
+ /* SERDES0 Initializations */
+ ret = Board_CfgSgmii_serdes0();
+ if(ret != BOARD_SOK)
+ {
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+Board_STATUS Board_serdesCfgSgmii_serdes1(void)
+{
+ Board_STATUS ret;
+
+ /* SERDES1 Initializations */
+ ret = Board_CfgSgmii_serdes1();
+ if(ret != BOARD_SOK)
+ {
+ return ret;
+ }
+
+ return BOARD_SOK;
}
/**
Can you please help me to double check if this patch can make two TDA4 EVM boads communication with SEDES0 LAN0 SGMII MAC to MAC mode.
or point out what I missed. Thanks very much.
I had dumped the SGMII register and SERDES register. If addition information need, please let me know.
A. SERDES1 LAN0 SGMII MAC to MAC wotked log and register dum;
B. SERDES0 LAN0 SGMII MAC to MAC faild log and register dump
