Interfacing simple LCD modules to framebuffer on TMS320C6A816x

B.J.

We are working on the HDVPSS TRM Doc. For the supporting small TFT LCD RGB display, are you talking about through on-chip HDMI display or directly hooking to DVO port? For the on-chip HDMI, team is still working on the SW to supports. For the directly connecting to the DVO port, you should able to do this after moving to PSP 04.00.00.09 release.

Regards,

yihe

Thanks for the response. I am talking about the DVO port for a small embedded display (like you might find on a cell phone -- maybe not even QVA resolution).

PSP 04.00.00.09 is not available yet, correct?

Any eta on that, or is it downloadable without the rest of the ezsdk?

Best regards,

B.J.

B.J.

PSP 04.00.00.09 was ready at last year,  it should be part of TI SDK 05.00.00.09(EA 1.4). You can download from TI site.

Regards,

yihe

I have:

ti-ezsdk_c6a816x-evm_5_00_00_56 (which shipped with the EVM this month)

It includes:

linux-2.6.34-psp04.00.00.07

Can you provide a download link for PSP 04.00.00.09?

Best regards,

B.J.

B.J,

TI is working on next EZSDK release, which will be available sometime next month.

We are also working with PSP team to see how releases can be accessed by customer directly.

Regards,

yihe

We too are looking to drive an LCD in addition to the HDMI output.  What documentation should I be looking at to configure the HDVPSS and what pins to connect the DVO to the LCD module?

Any further updates?

B.J.

Hi,

We will add the documentation for the same in our next set for release. Are you planning to driver LCD on the DVO2 venc of the HDVPSS or the DVO1 Venc of the HDVPSS. If you want to driver on the DVO2 VENC of HDVPSS then its fairly simple you have to connect the LCD to the RGB and sync pins of the DVO2 Venc. Set the clock and video timing parameters according to the LCD requirement using the sysfs entry

echo 74250,1280/110/220/40,720/5/20/5,1/3 > /sys/devices/platform/vpss/dvo2/timings

For DVO1 venc, currently HDVPSS firmware is configuring the pin mux for the on-chip HDMI and Linux drivers needs to make sure to override the configuration for the LCD pins.
 Again timings can be set according to LCD requirement on DVO1 also using the sysfs entry

echo 74250,1280/110/220/40,720/5/20/5,1/3 > /sys/devices/platform/vpss/hdmi/timings

Regards,
Hardik Shah  

So, are pins on VOUT0 (_r,g,b[2..9], HSYNC, VSYNC)  connected to DVO1 or DVO2?

Thanks for the info. Unfortunately, I don't know how to interpret these commands. Are the control strings for "/sys/devices/platform/vpss/dvo2/timings" documented anywhere?

For example, for a display module like http://www.trulydisplays.com/tft/specs/TFT240320-269-E(2.2D)v1.2.pdf with controller chip http://www.allshore.com/pdf/SAMSUNGS6D04H0X.pdf, which has a resolution of 240x320, how should the VPSS timing be configured? What other elements need to be configured to set the FB to 240x320?

I would want to be able to drive this FB and still be able to use the HDMI port at 720p or 1080p or other standard DVI resolutions.

Things are pretty clear for HDMI to a full-sized display. They are not clear for using an embedded display.

Best regards,

B.J.

VOUT0 is the same as DVO2 while VOUR1 is the smae as DVO1.

Regards,

yihe

/sys/devices/platform/vpss/display1/timings is a sysfs file entry.  Please refer the VPSS UserGuide to understand how this work. If you do not have such user guide, please let us know. But It should be part of the SDK packages.

Just like hardik said, in order to get 240x320 first, the DVO2 VENC need be programmed properly to generate the right timing to support that format.

Also the fb node need be programmed to have the right size to match the final output resolution, 240x320 for your case.

As for HDMI output, due to the current SW limitation, only 720p60/1080p60/1080i60/1080p30 format are supported.

what does embedded display mean? embedded sync?

Regards,

yihe

http://processors.wiki.ti.com/index.php/DM814X_C6A814X_AM387X_VPSS_Video_Driver_User_Guide_PSP_04.01.00.04

Do you have a more elaborate one available?

So, the two things I still find confusing are:

In the section "VPSS Library-display1: sysfs attributes", there is documentation for both "mode" and "timings". The "mode" parameter only talks about 1080p-60/1080p-30/1080i-60/720p-60. Obviously, this would not work for a small display. Can this parameter be ignored, or how does it need to be set? Does the "timings" attribute override it?

How do I compute the various front porch/back porch/sync-width parameters? Is this trivially determined from the display data sheet?

As far as "embedded display" goes, I mean a display module that is embedded in the product; not one intended to be connected externally using HDMI or DVI.

BTW, another question is how do we go about making the fb available early in the boot process so that a splash screen can be displayed (ideally from u-boot) so that the display is not just blank while the product is booting? It seems like the current framework makes this difficult? Or am I missing something.

Best regards,

B.J.

yihe said:

TI816X has the HDMI inside the chip, it is not external.

I understand this; I meant external to our product (e.g. plugged in via an HDMI cable via an HDMI cable) vs. an embedded display internal to our product. I did not mean external to the TI816x.

Best regards,

B.J.

Hi,

You can use either the mopde or the timing entry. mode is used for standarized displays like DVI, HDMI etc supporting various standards like VESA, CEA standards. Timing entry can be used for non-standard resolutions like LCD.  LCD data sheet should have all the values. If possible you can send the link to the LCD data sheet and we can suggest the values.

Regarding the availibility of the FB during boot time, you are correct we are not supporting this as of now.

Regards,

Hardik Shah

B.J.

Correct, the timings will be taken from the particular LCD datasheet.

BR

Steve

So, if you look at the datasheet I linked for the display that I am interested in, it appears that they want to see:

320 lines
240 pixels per line
VFP: 8
VBP: 8
HFP: 0
HBP: 0

There is no specification about the pixel clock.

So, can I use this with 0 FP/BP for the horizontal timing?

How do I calculate the pixel clock? Something like the following?

30 FPS x 240 pixels x 336 lines = 2419200
VSYNC >= 1 line
HSYNC = one pixel

The datasheet also specifies the maximum pixel clock as 10,000,000 Hz

echo 2419,240/0/0/1,320/8/8/240,1 > /sys/devices/platform/vpss/dvo2/timings

Is the vsync width specified in pixel clocks or is it specified in lines (the timings string I suggest above assumes pixel-clocks)?

Does this seem right?

Also, in the data sheet for the LCD controller chip, it says "Note.For RGB interface, VSYNC, HSYNC, DOTCLK should be supplied at much higher resolution than that of panel." Does this mean that my computed pixel clock is too slow?

Finally, the timings string that Hardik posted has an extra "/3" at the end of the string as compared to the format described in the VPSS driver documentation. What does that mean and is it important?

I hope that I am not being obtuse, but it is still not clear to me how to go from the datasheet to the timings string. Perhaps you can take a look at the datasheet and see if I have this right, or explain where it is wrong so that I can see the proper approach to take in case I wind up using a differnent LCD panel.

Thanks!

B.J.

B.J.

Vertical information is always in terms of lines, not pixels.

Can you send the LCD data sheet again please since I can't see it for some reason?

The pixel clock rate depends on what you want to set for the blanking periods. This allows you to have some control over the frame rate of the display.

You also need to know the horizontal and vertical sync widths, not just the front and back porch.

I think there may be an error somewhere since the front porch and back porch are usually not zero.

I need to see the data sheet to understand what it means by "should be supplied at a much higher resolution etc..."

I think your clock rate is way too low at 2419. This should be (Hactive + HFP + HSW + HBP) * (VActive + VFP + VSW + HBP) * 60, which would be closer to 4700. I doubt the LCD frame rate is as low as 30 fps. I could be wrong, but it is not very common.

You are heading in the right direction.

BR,

Steve

Thanks for the feedback. The panel controller data sheet is http://www.allshore.com/pdf/SAMSUNGS6D04H0X.pdf and the module data sheet is http://www.trulydisplays.com/tft/specs/TFT240320-269-E(2.2D)v1.2.pdf. It looks like the module data sheet does not have any relevant information; everything that appears to apply is in the controller datasheet.

As far as I can tell from the controller datasheet, the hsync width is one pixel clock, and the vertical sync width is 1 line, and there does not appear to be any horizontal front porch or back porch; but maybe I am reading it wrong...

Also, can you comment on what the "/3" at the end of the timing string that was posted in this thread means?

Thanks again,

B.J.

BJ,

Looking at figure 48 in the driver data sheet it shows that the horizontal front porch needs to be >5 pixels and the sync pulse is -ve and >= 1 clock. It is a little ambiguous on the back porch.

My recommendation would be to simply use something like, say, 16 for front/back/width just to make sure there is enough time for everything. This should not be an issue. Note the default sync polarities are positive, not negative so it will be necessary to invert the sync polarities. This is easy to do by setting register bits but I don't know if this is directly exposed in the sysfs entry.

Looking at figure 50 indicates that vertically VFP >= 3 and VBP >= 2

Section 3.5 describes a synchronized mode where the v-sync pulse resets an internal counter in the controller, then subsequent video data is written to the controller's internal memory. The idea being that you write to the memory faster than the LCD is reading it out. This is then reset at the next v-sync. The LCD uses an internal oscillator to read the data out to the actual display. I don't think this mode is what you want though.

I can't answer the /3 question, sorry. I have asked Hardik to respond to that.

BR,

Steve

B.J.

You do not need that "/3"

Regards,

yihe

B.J.

Hi !

yihe said:

As for HDMI output, due to the current SW limitation, only 720p60/1080p60/1080i60/1080p30 format are supported.

After this limitation is "removed" - which resolutions will be supported ? And when will this happend ? I need to connect "simple" and cheap PC Monitors - without adding extra cost due the use of an extra HDMI/DVI encoder (like the SiI9022 or TI's TFP410) added to VOUT0.

Thank You !

Regrads, Andy

Andy,

VOUT0 is kind of different with HDMI. For the VOUT0, we do support various mode or customized timing.

you can use /sys/devices/platform/vpss/display1/timings entry to configure VOUT0 timing to match your external monitors.

Regards,

yihe