Hi,
My customer wants to know PCIE clock input requirements (tR, tF).
Customer found Hardware Design Guide for KeyStone II Devices and there are table 6 and Figure 12 and 13.
https://www.tij.co.jp/jp/lit/an/sprabv0/sprabv0.pdf
These table and figures provide clock requirements for LJCB and SerDes/CML input buffers.
But it seems K2G12 uses LVDS buffer. What is clock requirements for LVDS buffer?
Thanks and regards,
Koichiro Tashiro