This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM6442: About General-Purpose Memory Controller (GPMC)

Part Number: AM6442

I am checking "12.3.3 General-Purpose Memory Controller (GPMC)" of AM64x TRM.
Please tell me about the following contents.

1. Which of (A) and (B) is the correct memory map for GPMC?
  (A) 2.1 MAIN Domain Memory Map
    GPMC0_CFG 0x3B000000 to 0x3B0003FF
    GPMC0_DATA 0x50000000 to 0x57FFFFFF
  (B) 12.3.3.4.12 GPMC Memory Regions
    GPMC0_CFG 0x05390000 to 0x053903FF
    GPMC0_DATA 0x20000000 to 0x27FFFFFF

2. Is the corresponding address (bit5-0: A29-A24) incorrect?
  The corresponding addresses are described as A29 to A24 in [bit5-0 BASE ADDRESS] of [13.3.3.6.17 GPMC_CONFIG7_i Register].
  For A29 to A24, the maximum address is 0x3F000000.
  In that case, GPMC0_DATA 0x50000000 to 0x57FFFFFF in Question 1- (B) cannot be specified.

3. Can I use 32bit data bus?
  There is no 32bit in [bit13-12 DEVICE SIZE] of [13.3.3.6.11 GPMC_CONFIG1_i Register].
    0h(R/W) = 8 bit
    1h(R/W) = 16 bit
    2h(R/W) = Reserved
    3h(R/W) = Reserved

  • Tomitama-san,

    1. Which of (A) and (B) is the correct memory map for GPMC?
      (A) 2.1 MAIN Domain Memory Map
        GPMC0_CFG 0x3B000000 to 0x3B0003FF
        GPMC0_DATA 0x50000000 to 0x57FFFFFF
      (B) 12.3.3.4.12 GPMC Memory Regions
        GPMC0_CFG 0x05390000 to 0x053903FF
        GPMC0_DATA 0x20000000 to 0x27FFFFFF

    (A) is correct for AM64xx memory map
        CSL_GPMC0_CFG_BASE  0x3b000000
        CSL_GPMC0_CFG_SIZE  0x00000400
        CSL_GPMC0_DATA_BASE 0x50000000
        CSL_GPMC0_DATA_SIZE 0x08000000

    (B) is correct for AM654x memory map

    2. Is the corresponding address (bit5-0: A29-A24) incorrect?
      The corresponding addresses are described as A29 to A24 in [bit5-0 BASE ADDRESS] of [13.3.3.6.17 GPMC_CONFIG7_i Register].
      For A29 to A24, the maximum address is 0x3F000000.
      In that case, GPMC0_DATA 0x50000000 to 0x57FFFFFF in Question 1- (B) cannot be specified.

    The system address of 0x50000000 uses 32 bits.
    The [bit5-0 BASE ADDRESS] field of GPMC_CONFIG7_i Register ignores bits 31 and 30 of the 32-bit address, and checks only bits [29-24]. Bits [5-0] corresponds to A29, A28, A27, A26, A25, and A24 of the 32-bit address.
    For example, for base addres 0x50000000 bits[5-0] = 010000b.
    31   30   29   28   27   26   25   24   23 ...
    0    1    0    1    0    0    0    0    0  ...

    The full GPMC range is accessible.

    3. Can I use 32bit data bus?
      There is no 32bit in [bit13-12 DEVICE SIZE] of [13.3.3.6.11 GPMC_CONFIG1_i Register].
        0h(R/W) = 8 bit
        1h(R/W) = 16 bit
        2h(R/W) = Reserved
        3h(R/W) = Reserved

    Yes, 32-bit data bus can be used with async modes and sync modes upto 100MHz GPMC_CLK.

    GPMC_CONFIG1_i Register [bits13-12 DEVICESIZE] = 2h(R/W) = 32 bit.
    The value of 2h = 32 bit should not be Reserved.

    I will file a bug against the TRM to remove the reserved and add a note to refer to the datasheet.

    I will also file a bug against the datasheet to clarify that 16-bit supports 133MHz synch mode but 32-bit supports 100MHz synch mode.

    It is advised to keep trace length to 4" to help to meet datasheet timings.

    Regards,
    Mark