PROCESSOR-SDK-J721E: TDA4 PCIe SRIS Issue

billy he

Hi,

Recently, we are trying to optimize PCIe RC/EP driver on TDA4, we find an important information in TDA4 TRM that TDA4 PCIe uses Separate Reference Clock with Independent Spread (SRIS) in default.

But we want to close this default configuration, making PCIe RC to produce reference clock to PCIe EP. So the questions I want to ask can be concluded as below:

1.If PCIe EP is provided with a reference clock from PCIe RC, the PCIe EP also has a SRIS internally, how can I confirm the clock source is the clock from RC or SRIS?

2.We notice that there is an register to close SRIS, does it work to change this bit in PCIe driver before link training?

3.If we close the SRIS configuration in PCIe driver and make PCIe RC to product reference clock to PCIe EP, can it work normally? Have you tried similar experiment?

over 4 years ago

0 jian35385 over 4 years ago

TI__Mastermind 23125 points

Billy,

I never test with this register enabled. But I am not sure if you need to set it based on what you goal here:

>>making PCIe RC to produce reference clock to PCIe EP

Since you are sending the clock from RC to EP, it seems you are trying to achieve common clock architecture instead of separate clock? note that you can still spread the refclk in the RC by enabling SSC clocking in the TDA4 PLL.

To answer your questions:

1. In this case you will leave the SRIS bit disabled (no spreading at EP), you would control the clock configurations as following:

RC: use internal PLL output as its SERDES refclk, also drive out refclk to the EP

EP: use external refclk as its SERDES refclk.

Note simply reading the clock mux registers in the EP will confirm you are using the RC clock.

2. see notes above.

3. Again, if you are going to use SRIS, you would want do the same on both of RC and EP - configure SERDES to use internal clocks on each side, enable SSC on the PLLs so they spread independently. In this case, you may need to enable the SRIS bit to accommodate jitters, and you may loose a few percent of performance due to the insertion of SKP symbols.

Please chime back if additional clarifications are needed.

regards

jian

0 billy he over 4 years ago in reply to jian35385

Prodigy 230 points

hi jian:

thanks for reply。

1：>>Since you are sending the clock from RC to EP, it seems you are trying to achieve common clock architecture instead of separate clock? note that you can still spread the refclk in the RC by enabling SSC clocking in the TDA4 PLL.

A: yes,we wan to use common clock architecture , and EP refclk from RC。Can we use common clock ？ if so, please tell me how to configure it.

also, we haved followed instruction remove R1,R2,R5,R6,install R3,R4,C1,C2。SOC_SERDES1_REFCLK_P/N signal is from RC through connector.We sure clcok signal from SOC_SERDES1_REFCLK_P/N is not working on EP board., because we found when cut off refclk line, RC still can linkup EP.so, EP is still using its own clock.

thanks.

0 jian35385 over 4 years ago in reply to billy he

TI__Mastermind 23125 points

Billy,

For 1.A, can you reference:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1004565/faq-tda4vm-tda4vm-dra829v-routing-pcie-reference-clock-externally?tisearch=e2e-sitesearch&keymatch=route%20pcie%20refclk#

Note that software patch to the driver is needed, beyond hardware resistor changes, to enable clock buffers. Please let me know if the FAQ page missed anything to answer your question fully.

thanks

Jian

0 Keerthy J over 4 years ago in reply to jian35385

TI__Guru**** 168880 points

Hi Billy,

Could you please post the latest status on this?

- Keerthy

0 billy he over 4 years ago in reply to Keerthy J

Prodigy 230 points

hi keerthy J

we have incorporate the patch provided by Jian into the SDK 7.3 code. and we haved did two experiments：

1: The two EVM boards are connected together by PCIe cable, the REFCLK+/REFCLK- lines of the PCIe link cable have been cut off。As we expected，in common clock mode, RC cannot recognize EP, but we found that RC can still recognize EP. How to explain this phenomenon?

. 2：EVM board connect to xavier by good PCIe cable, xavier as RC, provide 99.7kHz clock to tda4。The link status of pcie is very unstable, and it difficult to link up。

both experiments we haved check register value,and the result is same as require,but it seem not work.

#devmem2 0x00118094 reads 0x01000000 as expected.

#devmem2 0x00108078 read 0x00000100 as expected.

0 jian35385 over 4 years ago in reply to billy he

TI__Mastermind 23125 points

Billy,

On 1), it is likely that the EP PCIe driver is still using internal refclk that was generated within the SOC. So even the there is no clock signals on the cable, both ends of PCIe still functions as separate clocks.

On 2), I assume you meant the refclk from Xavier is 99.7MHz, If so, it seems the refclk is not meeting the PCIe spec, which specifies PCIe refclk must meet 300ppm jitter. But since we can are not sure that EP driver is using this refclk, we can not conclude the unstability is due to refclk.

Would you be able to test the RC and EP board separately:

1. Use the TDA4 EVM in RC mode, connect a standard NVME SSD to the board, and verify the link is functional and stable. Combined with the registers you verified, we can verify the RC is working and outputing refclk.

2. For EP testing, lets first verify the EP driver is configure using the common clock. i.e., verify that the EP SERDES is configured to use the cmn_refclk1 source input. To check, can you read the register values of SERDES_RST, address of this register is 0500040Ch for SERDES0, 0501040Ch for SERDES1,... and so on. If SERDESs are not configured to use external refclk, we may need to send you some patch to convert current PCIe EP driver to use externel refclk.

regards

Jian

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PROCESSOR-SDK-J721E: TDA4 PCIe SRIS Issue