Other Parts Discussed in Thread: AM1808
Normal 0 false false false EN-US X-NONE X-NONE
We are preparing a graphics demo to run on the Logic PD Zoom eval board for this processor.
We are having some trouble with LCD underflows. Here are the details:
1) Located graphics frame buffer(s) in external DDR2, base @ 0xc0000000
2) Used TI's own BSP code to configure LCD controller registers (raster mode).
3) In the master priority control registers, changed the LCD to highest priority (0). Left all other masters at the default priority.
Even with this change, we are seeing frequent LCD controller underflows, which permanently shifts the screen data. The questions are:
a) Do you have a recommended settings for all the master priorities to prevent LCD underflows? Any other configuration that might be incorrect and causing this problem?
b) When there is an LCD underflow, what is the best way to reset the LCD controller to get the screen data back into position?