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TDA4VM: 1CS 16Gb LPDDR4 config.

Moon SangHeuk
Prodigy 120 points

Part Number: TDA4VM

Hi.

I'm working on changing LPDDR4 32Gb to 16Gb,

but when using 16Gb LPDDR4, there's seems initialize issue.

Basic configurations.

* Schematic & PCB : schematic & PCB related DDR is same as EVK. (Micron 32Gb / 2 rank)

* LPDDR4 tested part :

        32Gb Micron / MT53D1024M32D4DT / 64Mb x 16DQ x 8 banks x 2 channels x 2 ranks

        16Gb : Hynix / H54G46BYYPX053      / 64Mb x 16DQ x 8 banks x 2 channels x 1 ranks (1CS)

 

* Test result

   32Gb LPDDR4 : No issues. System boot ok.

   16Gb LPDDR4 : frequency handshake timeout log displayed as below.

U-Boot SPL 2020.01 (May 18 2021 - 18:28:27 +0900)
SYSFW ABI: 3.1 (firmware rev 0x0015 '21.1.1--v2021.01a (Terrific Lla')
Reading on-board EEPROM at 0x50 failed 1
j721e_ddrss_probe(dev=41c87ca8)
j721e_ddrss_ofdata_to_priv(dev=41c87ca8)
fj721e_ddrss_power_on(ddrss=41cdca08)
LPDDR4_Probe: PASS
LPDDR4_Init: PASS
--->>> LPDDR4 Initialization is in progress ... <<<---
j721e_lpddr4_ack_freq_upd_req: received freq change req: req type = 1, req no. = 0
j721e_lpddr4_ack_freq_upd_req: received freq change req: req type = 0, req no. = 1
j721e_lpddr4_ack_freq_upd_req: received freq change req: req type = 1, req no. = 2
wait_for_bit_le32: Timeout (reg=114080 mask=80 wait_set=)
Timeout during frequency handshake
### ERROR ### Please RESET the board ###

I attached modified file. 

 uboot_diff_210512.zip

Is there any point of view for 1 rank LPDDR4?

Best regards.

S.H

  • 0
    TI__Mastermind 44270 points

    Hi,

    Can you please attach the DTSI file you are using for single rank / 16Gb memory?

    Does this issue occur if you use the same single rank configuration on the dual rank memory?

    Thanks,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 120 points

    Hi. Kevin.

    We used the DTSI file of the sdk7.3.(I will attached  that k3-j721e-ddr-evm-lp4-4266.dtsi file)
    how we can get the dtsi configue file?
    Can you support that?

    k3-j721e-ddr-evm-lp4-4266.zip

    Thanks!

  • 0 in reply to Moon SangHeuk
    Guru 10026 points

    Hi SangHyek

    We've provided your Embedded  S/W Team(Sunghwan Park) with DDR Config Tool.

    You need to find out the optimized timing parameter depending on your LPDDR4 selected. The tool is able to produce dtsi and header files to make new binary. 

    Also you need to contact memory vendor to check whether your SK Hynix memory will be compatible with JEDEC standard below.

    If the device meets the JEDEC standard, You can figure out the optimal value thru full verification in your application level.

    Thanks.

    Regards

    Jack