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AM6442: About General-Purpose Memory Controller (GPMC)

tomitama
Expert 1090 points
Part Number: AM6442

I have two questions.

About "12.3.3 General-Purpose Memory Controller (GPMC)" of AM64x TRM.
1. Can I use "non-multiplexed Address Data 32-Bit Device"?
  [12.3.3.2.2 GPMC I / O Signals] [Table 12-1885. GPMC Pin Multiplexing Options] provides an example of "non-multiplexed Address Data 16-Bit Device".
  Please let me know if "non-multiplexed Address Data 32-Bit Device" can also be used.
  In that case, is it okay for 32-bit data to be GPMC0_AD [31] to GPMC0_AD [0]?

About "7.10.5.8 GPMC" of AM64x data sheet.
2. Can I use FCLK other than GPMC's 100MHz and 133MHz?
  For example, can it be used even if FCLK is set to 50MHz, which is smaller than 100MHz?

  • +1
    TI__Mastermind 30110 points

    Hi,

    Sorry for the late reply.

    tomitama said:
    About "12.3.3 General-Purpose Memory Controller (GPMC)" of AM64x TRM.
    1. Can I use "non-multiplexed Address Data 32-Bit Device"?

    Yes. With AM644x, GPMC supports "non-multiplexed Address Data 32-Bit Device". The address bus is the same as "non-multiplexed Address Data 16-Bit Device", except both A1 and A0 are not used. The GPMC0_AD[31:0] bus contains the 32-bit data.

    I refer to "non-multiplexed Address Data 16-Bit Device" from Table 12-1885. GPMC Pin Multiplexing Options.

    tomitama said:
    About "7.10.5.8 GPMC" of AM64x data sheet.
    2. Can I use FCLK other than GPMC's 100MHz and 133MHz?

    Yes. Slower FCLK frequencies may be used.

    100MHz and 133MHz are the fastest frequencies of the two clock sources that can be provided to GPMC_FCLK.
    The CTRLMMR_GPMC_CLKSEL register selects the GPMC clock source
    0h - MAIN_PLL0_HSDIV3_CLKOUT
    1h - MAIN_PLL2_HSDIV3_CLKOUT
    Refer to TRM 6.1.1.5.101 CTRLMMR_GPMC_CLKSEL Register

    You also have the clock divider inside GPMC that could be used to divide the GPMC0_CLK from GPMC_FCLK by a factor of 1,2,3, or 4. See 13.3.3.6.11 GPMC_CONFIG1_i Register[1:0] GPMCFCLKDIVIDER.

    FYI - You can route the selected GPMC_FCLK to the GPMC0_CLK pin instead of the GPMC0_CLK signal from the GPMC module. The GPMC0_CLK stops between transfers, but the GPMC_FCLK runs continuously. Select the GPMC_FCLK by setting MUXMODE to 4 (GPMC0_FCLK_MUX) instead of 0 (GPMC0_CLK) in the PADCONFIG31 register.
    Refer to Datasheet Table 6-77. Pin Multiplexing
    When using the the free-running GPMC0_FCLK_MUX with synchronous transfers, the GPMC should keep GPMCFCLKDIVIDER = 0 (div-by-1).

    Regards,
    Mark