Hello,
for debugging and validation purpose, we are trying to observe the clock signals generated by both PLLs on OMAPL138. We can successfully monitor the CLKOUT Pin for
every SYSCLK generated by PLLC0. Unfortunately, on the converse, we can't observe any of the clocks generated by PLLC1.
By referencing OMAP-L138 Applications Processor System Reference Guide, configuration register are setup as follows:
* PINMUX13_7_4 was set to 0x1 to enable CLKOUT as an output pin
* PLLC0 OBSCLK Select Register (OCSEL) was set to 0x1E to select PLLC1 OBSCLK as the probed clock
* PLLC1 OBSCLK Select Register (OCSEL) was set to any value between 0x14 and 0x19 with no appreciable result
We also applied different values to Oscillator Divider 1 Register (OSCDIV), also taking care of OD1EN bit and OBSEN bit in the clock enable control register (CKEN).
Let me finally point out that this appear to relate only to the "observation clock" feature, since the real clocks are correctly generated and working for the attached peripherals. Just wanted to know if anyone else noticed the same. Already searched for errata and dig the forum but found nothing on this.
Thanks in advance,
Regards,
Andrea
