TDA4VM: How to generate MSI Interrupt from Root complex to Endpoint(PCIe)

gangadhar Vasamsetti

Part Number: TDA4VM

Hi,

I am using TDA4VMXEVM board.

In pci-epf-test.c file using pci_epf_test_raise_irq() func we are able to generate MSI interrupt from End point to Root Complex

Same way from pci_endpoint_test.c file I want to generate MSI interrupt from Root complex to End point

1. Is it possible to generate MSI interrupt from Root complex to End point ?

2. Any sample source code is available?

3. Does any changes required in DTS file ? if yes what are those changes ?

4. Please let me what are changes required in platform driver files

5. Any other ways we can generate interrupt from Root complex to end point ?

Thanks

Gangadhar

over 4 years ago

0 jian35385 over 4 years ago

TI__Mastermind 23125 points

Gangadhar,

MSI/X is only defined for EP to raise interrupt to RC. So there is way to generate MSI from RC to EP.

There are vendor-specific mechanisms to generate interrupt by RC, as documented in TRM:
12.2.3.4.11.3 PCIe Interrupt Generation in RP Mode

please let me know if you have further questions.

regards

Jian

0 gangadhar Vasamsetti over 4 years ago in reply to jian35385

Intellectual 435 points

Hi Jain,

I am referring this link https://www.ti.com/lit/zip/spruil1 , there is no section available "12.2.3.4.11.3".

Could you please send me the latest TRM document link.

thanks

Gangadhar

0 gangadhar Vasamsetti over 4 years ago in reply to gangadhar Vasamsetti

Intellectual 435 points

Hi Jain,

I have got it in TRM,

Thanks for you reply.

Thanks

Gangahdar

0 gangadhar Vasamsetti over 4 years ago in reply to gangadhar Vasamsetti

Intellectual 435 points

Hi Jain

As I understood,

F0_VSEC_INTERRUPT_OUT, that can be used for RC to trigger an interrupt to EP.

To enable F0_VSEC_INTERRUPT_OUT signals at RP side we need to set HTI and VSEC_Count so the value would be 0x300 in PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG.

This register will trigger PCIE_DOWNSTREAM_PULSE interrupt to the EP side

How to check PCIE_DOWNSTREAM_PULSE interrupt at the EP side?

Could you please provide more information and sample source code?

Thanks

Gangadhar

0 gangadhar Vasamsetti over 4 years ago in reply to gangadhar Vasamsetti

Intellectual 435 points

Hi Jain,

As per my understanding required changes are

RC side: -

In this PCIE_CORE_PFn_I_VENDOR_SPECIFIC_CONTROL_REG() register written the value is 0x300

EP side:-

To enable PCIE_DOWNSTREAM_PULSE by writing “1” in register PCIE_INTD_ENABLE_REG_SYS_0 [Bit 0]

and in dts file GIC_SPI changes added.

Please let me know further changes.

Thanks

Gangadhar

0 jian35385 over 4 years ago in reply to gangadhar Vasamsetti

TI__Mastermind 23125 points

Ganadhar,

The steps you described are correct. you can refer to a similar topic at:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/901265/how-to-use-tda4-pcie-s-vendor-specific-capability-vsec/3342956?tisearch=e2e-sitesearch&keymatch=F0_VSEC_INTERRUPT_OUT#3342956

where the user was able to see the interrupt being generated.

Regards

Jian

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TDA4VM: How to generate MSI Interrupt from Root complex to Endpoint(PCIe)